Lines Matching +full:lpddr4 +full:- +full:channel
1 // SPDX-License-Identifier: MIT
35 DRAM_TYPE_STR(LPDDR4), in intel_dram_type_str()
50 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); in pnv_detect_mem_freq()
54 dev_priv->fsb_freq = 533; /* 133*4 */ in pnv_detect_mem_freq()
57 dev_priv->fsb_freq = 800; /* 200*4 */ in pnv_detect_mem_freq()
60 dev_priv->fsb_freq = 667; /* 167*4 */ in pnv_detect_mem_freq()
63 dev_priv->fsb_freq = 400; /* 100*4 */ in pnv_detect_mem_freq()
69 dev_priv->mem_freq = 533; in pnv_detect_mem_freq()
72 dev_priv->mem_freq = 667; in pnv_detect_mem_freq()
75 dev_priv->mem_freq = 800; in pnv_detect_mem_freq()
80 tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL); in pnv_detect_mem_freq()
81 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; in pnv_detect_mem_freq()
88 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); in ilk_detect_mem_freq()
91 dev_priv->mem_freq = 800; in ilk_detect_mem_freq()
94 dev_priv->mem_freq = 1066; in ilk_detect_mem_freq()
97 dev_priv->mem_freq = 1333; in ilk_detect_mem_freq()
100 dev_priv->mem_freq = 1600; in ilk_detect_mem_freq()
103 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n", in ilk_detect_mem_freq()
105 dev_priv->mem_freq = 0; in ilk_detect_mem_freq()
109 csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0); in ilk_detect_mem_freq()
112 dev_priv->fsb_freq = 3200; in ilk_detect_mem_freq()
115 dev_priv->fsb_freq = 3733; in ilk_detect_mem_freq()
118 dev_priv->fsb_freq = 4266; in ilk_detect_mem_freq()
121 dev_priv->fsb_freq = 4800; in ilk_detect_mem_freq()
124 dev_priv->fsb_freq = 5333; in ilk_detect_mem_freq()
127 dev_priv->fsb_freq = 5866; in ilk_detect_mem_freq()
130 dev_priv->fsb_freq = 6400; in ilk_detect_mem_freq()
133 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", in ilk_detect_mem_freq()
135 dev_priv->fsb_freq = 0; in ilk_detect_mem_freq()
150 i915->mem_freq = 2000; in chv_detect_mem_freq()
153 i915->mem_freq = 1600; in chv_detect_mem_freq()
169 i915->mem_freq = 800; in vlv_detect_mem_freq()
172 i915->mem_freq = 1066; in vlv_detect_mem_freq()
175 i915->mem_freq = 1333; in vlv_detect_mem_freq()
191 if (i915->mem_freq) in detect_mem_freq()
192 drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); in detect_mem_freq()
197 return dimm->ranks * 64 / (dimm->width ?: 1); in intel_dimm_num_devices()
270 return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16; in skl_is_16gb_dimm()
276 int channel, char dimm_name, u16 val) in skl_dram_get_dimm_info() argument
279 dimm->size = icl_get_dimm_size(val); in skl_dram_get_dimm_info()
280 dimm->width = icl_get_dimm_width(val); in skl_dram_get_dimm_info()
281 dimm->ranks = icl_get_dimm_ranks(val); in skl_dram_get_dimm_info()
283 dimm->size = skl_get_dimm_size(val); in skl_dram_get_dimm_info()
284 dimm->width = skl_get_dimm_width(val); in skl_dram_get_dimm_info()
285 dimm->ranks = skl_get_dimm_ranks(val); in skl_dram_get_dimm_info()
288 drm_dbg_kms(&i915->drm, in skl_dram_get_dimm_info()
290 channel, dimm_name, dimm->size, dimm->width, dimm->ranks, in skl_dram_get_dimm_info()
297 int channel, u32 val) in skl_dram_get_channel_info() argument
299 skl_dram_get_dimm_info(i915, &ch->dimm_l, in skl_dram_get_channel_info()
300 channel, 'L', val & 0xffff); in skl_dram_get_channel_info()
301 skl_dram_get_dimm_info(i915, &ch->dimm_s, in skl_dram_get_channel_info()
302 channel, 'S', val >> 16); in skl_dram_get_channel_info()
304 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) { in skl_dram_get_channel_info()
305 drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel); in skl_dram_get_channel_info()
306 return -EINVAL; in skl_dram_get_channel_info()
309 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2) in skl_dram_get_channel_info()
310 ch->ranks = 2; in skl_dram_get_channel_info()
311 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1) in skl_dram_get_channel_info()
312 ch->ranks = 2; in skl_dram_get_channel_info()
314 ch->ranks = 1; in skl_dram_get_channel_info()
316 ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) || in skl_dram_get_channel_info()
317 skl_is_16gb_dimm(&ch->dimm_s); in skl_dram_get_channel_info()
319 drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n", in skl_dram_get_channel_info()
320 channel, ch->ranks, str_yes_no(ch->is_16gb_dimm)); in skl_dram_get_channel_info()
330 (ch0->dimm_s.size == 0 || in intel_is_dram_symmetric()
331 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l))); in intel_is_dram_symmetric()
337 struct dram_info *dram_info = &i915->dram_info; in skl_dram_get_channels_info()
342 val = intel_uncore_read(&i915->uncore, in skl_dram_get_channels_info()
346 dram_info->num_channels++; in skl_dram_get_channels_info()
348 val = intel_uncore_read(&i915->uncore, in skl_dram_get_channels_info()
352 dram_info->num_channels++; in skl_dram_get_channels_info()
354 if (dram_info->num_channels == 0) { in skl_dram_get_channels_info()
355 drm_info(&i915->drm, "Number of memory channels is zero\n"); in skl_dram_get_channels_info()
356 return -EINVAL; in skl_dram_get_channels_info()
360 drm_info(&i915->drm, "couldn't get memory rank information\n"); in skl_dram_get_channels_info()
361 return -EINVAL; in skl_dram_get_channels_info()
364 dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm; in skl_dram_get_channels_info()
366 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1); in skl_dram_get_channels_info()
368 drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n", in skl_dram_get_channels_info()
369 str_yes_no(dram_info->symmetric_memory)); in skl_dram_get_channels_info()
379 val = intel_uncore_read(&i915->uncore, in skl_get_dram_type()
400 struct dram_info *dram_info = &i915->dram_info; in skl_get_dram_info()
403 dram_info->type = skl_get_dram_type(i915); in skl_get_dram_info()
404 drm_dbg_kms(&i915->drm, "DRAM type: %s\n", in skl_get_dram_info()
405 intel_dram_type_str(dram_info->type)); in skl_get_dram_info()
482 dimm->width = bxt_get_dimm_width(val); in bxt_get_dimm_info()
483 dimm->ranks = bxt_get_dimm_ranks(val); in bxt_get_dimm_info()
487 * Gb to match the way we report this for non-LP platforms. in bxt_get_dimm_info()
489 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm); in bxt_get_dimm_info()
494 struct dram_info *dram_info = &i915->dram_info; in bxt_get_dram_info()
506 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i)); in bxt_get_dram_info()
510 dram_info->num_channels++; in bxt_get_dram_info()
515 drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN && in bxt_get_dram_info()
516 dram_info->type != INTEL_DRAM_UNKNOWN && in bxt_get_dram_info()
517 dram_info->type != type); in bxt_get_dram_info()
519 drm_dbg_kms(&i915->drm, in bxt_get_dram_info()
521 i - BXT_D_CR_DRP0_DUNIT_START, in bxt_get_dram_info()
529 dram_info->type = type; in bxt_get_dram_info()
532 if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) { in bxt_get_dram_info()
533 drm_info(&i915->drm, "couldn't get memory information\n"); in bxt_get_dram_info()
534 return -EINVAL; in bxt_get_dram_info()
542 struct dram_info *dram_info = &dev_priv->dram_info; in icl_pcode_read_mem_global_info()
546 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in icl_pcode_read_mem_global_info()
554 dram_info->type = INTEL_DRAM_DDR4; in icl_pcode_read_mem_global_info()
557 dram_info->type = INTEL_DRAM_DDR5; in icl_pcode_read_mem_global_info()
560 dram_info->type = INTEL_DRAM_LPDDR5; in icl_pcode_read_mem_global_info()
563 dram_info->type = INTEL_DRAM_LPDDR4; in icl_pcode_read_mem_global_info()
566 dram_info->type = INTEL_DRAM_DDR3; in icl_pcode_read_mem_global_info()
569 dram_info->type = INTEL_DRAM_LPDDR3; in icl_pcode_read_mem_global_info()
573 return -EINVAL; in icl_pcode_read_mem_global_info()
578 dram_info->type = INTEL_DRAM_DDR4; in icl_pcode_read_mem_global_info()
581 dram_info->type = INTEL_DRAM_DDR3; in icl_pcode_read_mem_global_info()
584 dram_info->type = INTEL_DRAM_LPDDR3; in icl_pcode_read_mem_global_info()
587 dram_info->type = INTEL_DRAM_LPDDR4; in icl_pcode_read_mem_global_info()
591 return -EINVAL; in icl_pcode_read_mem_global_info()
595 dram_info->num_channels = (val & 0xf0) >> 4; in icl_pcode_read_mem_global_info()
596 dram_info->num_qgv_points = (val & 0xf00) >> 8; in icl_pcode_read_mem_global_info()
597 dram_info->num_psf_gv_points = (val & 0x3000) >> 12; in icl_pcode_read_mem_global_info()
614 i915->dram_info.wm_lv_0_adjust_needed = false; in gen12_get_dram_info()
621 u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); in xelpdp_get_dram_info()
622 struct dram_info *dram_info = &i915->dram_info; in xelpdp_get_dram_info()
626 dram_info->type = INTEL_DRAM_DDR4; in xelpdp_get_dram_info()
629 dram_info->type = INTEL_DRAM_DDR5; in xelpdp_get_dram_info()
632 dram_info->type = INTEL_DRAM_LPDDR5; in xelpdp_get_dram_info()
635 dram_info->type = INTEL_DRAM_LPDDR4; in xelpdp_get_dram_info()
638 dram_info->type = INTEL_DRAM_DDR3; in xelpdp_get_dram_info()
641 dram_info->type = INTEL_DRAM_LPDDR3; in xelpdp_get_dram_info()
645 return -EINVAL; in xelpdp_get_dram_info()
648 dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val); in xelpdp_get_dram_info()
649 dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val); in xelpdp_get_dram_info()
657 struct dram_info *dram_info = &i915->dram_info; in intel_dram_detect()
669 dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915); in intel_dram_detect()
684 drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels); in intel_dram_detect()
686 drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n", in intel_dram_detect()
687 str_yes_no(dram_info->wm_lv_0_adjust_needed)); in intel_dram_detect()
707 edram_cap = intel_uncore_read_fw(&i915->uncore, HSW_EDRAM_CAP); in intel_dram_edram_detect()
719 i915->edram_size_mb = 128; in intel_dram_edram_detect()
721 i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap); in intel_dram_edram_detect()
723 drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb); in intel_dram_edram_detect()