Lines Matching +full:south +full:- +full:field
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
44 * registers that are defined solely for the use by function-like macros.
52 * should be defined using function-like macros.
58 * with underscore, followed by a function-like macro choosing the right
61 * Define the register contents (i.e. bit and bit field macros) from most
65 * Define bit fields using ``REG_GENMASK(h, l)``. Define bit field contents
68 * function-like macros may be used to define bit fields, but do note that the
87 * Try to re-use existing register macro definitions. Only add new macros for
95 * When a bit (field) macro changes or gets added for a new platform, while
206 #define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
553 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
556 (BXT_PHY_BASE(phy) + _PIPE((ch), (reg_ch0) - _BXT_PHY0_BASE, \
557 (reg_ch1) - _BXT_PHY0_BASE))
841 * [0-7] @ 0x2000 gen2,gen3
842 * [8-15] @ 0x3000 945,g33,pnv
844 * [0-15] @ 0x3000 gen4,gen5
846 * [0-15] @ 0x100000 gen6,vlv,chv
847 * [0-31] @ 0x100000 gen7+
852 #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
860 #define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
889 #define PRB0_BASE (0x2030 - 0x30)
890 #define PRB1_BASE (0x2040 - 0x30) /* 830,gen3 */
891 #define PRB2_BASE (0x2050 - 0x30) /* gen3 */
892 #define SRB0_BASE (0x2100 - 0x30) /* gen2 */
893 #define SRB1_BASE (0x2110 - 0x30) /* gen2 */
894 #define SRB2_BASE (0x2120 - 0x30) /* 830 */
895 #define SRB3_BASE (0x2130 - 0x30) /* 830 */
960 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
961 #define HECI_FWSTS(base, x) _MMIO((base) + _PICK(x, -(base), \
1044 #define DISPLAY_PLANE_FLIP_PENDING(plane) (1 << (11 - (plane))) /* A and B only */
1126 /* Enables non-sequential data reads through arbiter
1135 /* Arbiter time slice for non-isoch streams */
1169 * These defines should cover us well from SNB->HSW with minor exceptions
1208 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
1243 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \
1323 #define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */
1325 #define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */
1329 #define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */
1355 #define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */
1470 #define PHY_STATUS_CMN_LDO(phy, ch) (1 << (6 - (6 * (phy) + 3 * (ch))))
1471 #define PHY_STATUS_SPLINE_LDO(phy, ch, spline) (1 << (8 - (6 * (phy) + 3 * (ch) + (spline)…
1475 * this field (only one bit may be set).
1480 /* i830, required in DVO non-gang */
1492 # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x) - 1) << 9)
1540 * This register field has values of multiplication factor minus 1, with
1594 # define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1595 # define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1596 # define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1597 # define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1598 # define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1599 # define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1600 # define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1601 # define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1602 # define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1603 # define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1604 # define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1605 # define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1611 # define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1612 # define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1713 #define PFI_CREDIT(x) (((x) - 8) << 28) /* 8-15 */
1729 /* pre-i965 10bit interpolated mode ldw */
1733 /* pre-i965 10bit interpolated mode udw */
2111 #define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2265 * Programmed value is multiplier - 1, up to 5x.
2313 * of the infoframe structure specified by CEA-861. */
2368 #define PFIT_VERT_INTERP_MASK REG_GENMASK(11, 10) /* pre-965 */
2370 #define PFIT_VERT_AUTO_SCALE REG_BIT(9) /* pre-965 */
2371 #define PFIT_HORIZ_INTERP_MASK REG_GENMASK(7, 6) /* pre-965 */
2373 #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */
2374 #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */
2377 #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */
2379 #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */
2410 /* Link training mode - select a suitable mode for each stage */
2434 /* Signal pre-emphasis levels, like voltages, the other end tells us what
2445 #define DP_PORT_WIDTH(width) (((width) - 1) << 19)
2498 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2500 #define TU_SIZE(x) REG_FIELD_PREP(TU_SIZE_MASK, (x) - 1) /* default size 64 */
2516 * Attributes and VB-ID.
2537 #define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
2540 #define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
2541 …CONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
2545 #define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
2548 #define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
2559 * DBL=power saving pixel doubling, PF-ID* requires panel fitter
2575 #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
2576 … TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
2577 …RANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
2578 …RANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
2580 #define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
2609 #define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL << 18) /* pre-965 */
2632 #define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL << 2) /* pre-965 */
2669 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
2671 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
2819 #define DSPFW_PLANEC_OLD_MASK (0x7f << 0) /* pre-gen4 sprite C */
3043 #define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2…
3168 #define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
3339 #define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 …
3525 _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
3543 #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)…
3553 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
3597 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
3600 * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition
3601 * expanded to include bit 23 as well. However, the shift-24 based values
3604 #define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */
3623 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
3638 #define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */
3648 #define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */
3729 #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */
3731 #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */
3956 #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
3957 #define DIGITAL_PORTA_PULSE_DURATION_4_5ms (1 << 2) /* pre-HSW */
3958 #define DIGITAL_PORTA_PULSE_DURATION_6ms (2 << 2) /* pre-HSW */
3959 #define DIGITAL_PORTA_PULSE_DURATION_100ms (3 << 2) /* pre-HSW */
3960 #define DIGITAL_PORTA_PULSE_DURATION_MASK (3 << 2) /* pre-HSW */
4058 #define PS_SCALER_MODE_MASK REG_BIT(29) /* glk-tgl */
4074 #define PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-lin…
4086 #define PS_BINDING_Y_MASK REG_GENMASK(7, 5) /* icl-tgl */
4253 #define GAMMA_MODE_MODE_SPLIT REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* ivb-bdw */
4254 #define GAMMA_MODE_MODE_12BIT_MULTI_SEG REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 3) /* icl-tgl */
4407 #define _HPD_PIN_DDI(hpd_pin) ((hpd_pin) - HPD_PORT_A)
4408 #define _HPD_PIN_TC(hpd_pin) ((hpd_pin) - HPD_PORT_TC1)
4552 /* Required on all Ironlake and Sandybridge according to the B-Spec. */
4755 /* south display engine interrupt: IBX */
4796 /* south display engine interrupt: CPT - CNP */
4844 /* south display engine interrupt: ICP/TGP/MTP */
4879 #define PORTD_PULSE_DURATION_2ms (0 << 18) /* pre-LPT */
4880 #define PORTD_PULSE_DURATION_4_5ms (1 << 18) /* pre-LPT */
4881 #define PORTD_PULSE_DURATION_6ms (2 << 18) /* pre-LPT */
4882 #define PORTD_PULSE_DURATION_100ms (3 << 18) /* pre-LPT */
4883 #define PORTD_PULSE_DURATION_MASK (3 << 18) /* pre-LPT */
4890 #define PORTC_PULSE_DURATION_2ms (0 << 10) /* pre-LPT */
4891 #define PORTC_PULSE_DURATION_4_5ms (1 << 10) /* pre-LPT */
4892 #define PORTC_PULSE_DURATION_6ms (2 << 10) /* pre-LPT */
4893 #define PORTC_PULSE_DURATION_100ms (3 << 10) /* pre-LPT */
4894 #define PORTC_PULSE_DURATION_MASK (3 << 10) /* pre-LPT */
4901 #define PORTB_PULSE_DURATION_2ms (0 << 2) /* pre-LPT */
4902 #define PORTB_PULSE_DURATION_4_5ms (1 << 2) /* pre-LPT */
4903 #define PORTB_PULSE_DURATION_6ms (2 << 2) /* pre-LPT */
4904 #define PORTB_PULSE_DURATION_100ms (3 << 2) /* pre-LPT */
4905 #define PORTB_PULSE_DURATION_MASK (3 << 2) /* pre-LPT */
5034 /* Per-transcoder DIP controls (PCH) */
5050 /* Per-transcoder DIP controls (VLV) */
5172 #define TRANS_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
5195 …CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
5212 #define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
5213 #define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
5262 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AU…
5263 #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_…
5273 #define TRANS_DP_PORT_SEL(port) REG_FIELD_PREP(TRANS_DP_PORT_SEL_MASK, (port) - PORT_B)
5308 /* SNB A-stepping */
5313 /* SNB B-stepping */
5370 #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
5443 /* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
5446 /* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
5469 /* These are the 4 32-bit write offset registers for each stream
5476 * HSW - ICL power wells
5480 * - main (HSW_PWR_WELL_CTL[1-4])
5481 * - AUX (ICL_PWR_WELL_CTL_AUX[1-4])
5482 * - DDI (ICL_PWR_WELL_CTL_DDI[1-4])
5485 * - BIOS (HSW_PWR_WELL_CTL1/ICL_PWR_WELL_CTL_AUX1/ICL_PWR_WELL_CTL_DDI1)
5486 * - DRIVER (HSW_PWR_WELL_CTL2/ICL_PWR_WELL_CTL_AUX2/ICL_PWR_WELL_CTL_DDI2)
5487 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)
5488 * - DEBUG (HSW_PWR_WELL_CTL4/ICL_PWR_WELL_CTL_AUX4/ICL_PWR_WELL_CTL_DDI4)
5513 /* ICL/TGL - power wells */
5520 /* XE_LPD - power wells */
5572 /* HSW - power well misc debug registers */
5592 * SKL_DISP_PW1_IDX..SKL_DISP_PW2_IDX -> PG1..PG2
5595 ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1)
5598 * ICL_DISP_PW1_IDX..ICL_DISP_PW4_IDX -> PG1..PG4
5601 ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1)
5602 #define SKL_FUSE_PG_DIST_STATUS(pg) (1 << (27 - (pg)))
5604 #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A)
5613 /* Per-pipe DDI Function Control */
5664 #define TRANS_DDI_PORT_WIDTH(width) REG_FIELD_PREP(TRANS_DDI_PORT_WIDTH_MASK, (width) - 1)
5740 #define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 : ((width) - 1)) << 1)
5838 #define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
6019 #define DPLL_CFGCR1(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR1, _DPLL2_CFGCR1)
6020 #define DPLL_CFGCR2(id) _MMIO_PIPE((id) - SKL_DPLL1, _DPLL1_CFGCR2, _DPLL2_CFGCR2)
6028 (tc_port) - TC_PORT_4 + 21))
6111 /* ADL-P Type C PLL */
6202 /* For ADL-S DPLL4_CFGCR0/1 are used to control DPLL2 */
6246 /* Pipe WM_LINETIME - watermark line time */
6286 #define CSC_POSITION_BEFORE_GAMMA (1 << 1) /* pre-glk */