Lines Matching +full:0 +full:x4f000

106  *  #define _FOO_A                      0xf000
107  *  #define _FOO_B                      0xf001
111  *  #define   FOO_MODE_BAR              REG_FIELD_PREP(FOO_MODE_MASK, 0)
115  *  #define BAR                         _MMIO(0xb000)
116  *  #define GEN8_BAR                    _MMIO(0xb888)
119 #define GU_CNTL_PROTECTED		_MMIO(0x10100C)
122 #define GU_CNTL				_MMIO(0x101010)
125 #define GU_DEBUG			_MMIO(0x101018)
128 #define GEN6_STOLEN_RESERVED		_MMIO(0x1082C0)
129 #define GEN6_STOLEN_RESERVED_ADDR_MASK	(0xFFF << 20)
130 #define GEN7_STOLEN_RESERVED_ADDR_MASK	(0x3FFF << 18)
132 #define GEN6_STOLEN_RESERVED_1M		(0 << 4)
137 #define GEN7_STOLEN_RESERVED_1M		(0 << 5)
140 #define GEN8_STOLEN_RESERVED_1M		(0 << 7)
144 #define GEN6_STOLEN_RESERVED_ENABLE	(1 << 0)
145 #define GEN11_STOLEN_RESERVED_ADDR_MASK	(0xFFFFFFFFFFFULL << 20)
147 #define _VGA_MSR_WRITE _MMIO(0x3c2)
149 #define _GEN7_PIPEA_DE_LOAD_SL	0x70068
150 #define _GEN7_PIPEB_DE_LOAD_SL	0x71068
156 #define DEBUG_RESET_I830		_MMIO(0x6070)
164 #define VLV_IOSF_DOORBELL_REQ			_MMIO(VLV_DISPLAY_BASE + 0x2100)
170 #define   IOSF_SB_BUSY				(1 << 0)
171 #define   IOSF_PORT_BUNIT			0x03
172 #define   IOSF_PORT_PUNIT			0x04
173 #define   IOSF_PORT_NC				0x11
174 #define   IOSF_PORT_DPIO			0x12
175 #define   IOSF_PORT_GPIO_NC			0x13
176 #define   IOSF_PORT_CCK				0x14
177 #define   IOSF_PORT_DPIO_2			0x1a
178 #define   IOSF_PORT_FLISDSI			0x1b
179 #define   IOSF_PORT_GPIO_SC			0x48
180 #define   IOSF_PORT_GPIO_SUS			0xa8
181 #define   IOSF_PORT_CCU				0xa9
182 #define   CHV_IOSF_PORT_GPIO_N			0x13
183 #define   CHV_IOSF_PORT_GPIO_SE			0x48
184 #define   CHV_IOSF_PORT_GPIO_E			0xa8
185 #define   CHV_IOSF_PORT_GPIO_SW			0xb2
186 #define VLV_IOSF_DATA				_MMIO(VLV_DISPLAY_BASE + 0x2104)
187 #define VLV_IOSF_ADDR				_MMIO(VLV_DISPLAY_BASE + 0x2108)
190 #define DPIO_DEVFN			0
192 #define DPIO_CTL			_MMIO(VLV_DISPLAY_BASE + 0x2110)
196 #define  DPIO_CMNRST			(1 << 0)
203 #define _VLV_PLL_DW3_CH0		0x800c
205 #define   DPIO_POST_DIV_DAC		0
215 #define   DPIO_M2DIV_MASK		0xff
216 #define _VLV_PLL_DW3_CH1		0x802c
219 #define _VLV_PLL_DW5_CH0		0x8014
222 #define   DPIO_BIAS_CURRENT_CTL_SHIFT	21 /* 3 bits, always 0x7 */
225 #define   DPIO_DRIVER_CTL_SHIFT		12 /* always set to 0x8 */
226 #define   DPIO_CLK_BIAS_CTL_SHIFT	8 /* always set to 0x5 */
227 #define _VLV_PLL_DW5_CH1		0x8034
230 #define _VLV_PLL_DW7_CH0		0x801c
231 #define _VLV_PLL_DW7_CH1		0x803c
234 #define _VLV_PLL_DW8_CH0		0x8040
235 #define _VLV_PLL_DW8_CH1		0x8060
238 #define VLV_PLL_DW9_BCAST		0xc044
239 #define _VLV_PLL_DW9_CH0		0x8044
240 #define _VLV_PLL_DW9_CH1		0x8064
243 #define _VLV_PLL_DW10_CH0		0x8048
244 #define _VLV_PLL_DW10_CH1		0x8068
247 #define _VLV_PLL_DW11_CH0		0x804c
248 #define _VLV_PLL_DW11_CH1		0x806c
252 #define VLV_REF_DW13			0x80ac
254 #define VLV_CMN_DW0			0x8100
260 #define _VLV_PCS_DW0_CH0		0x8200
261 #define _VLV_PCS_DW0_CH1		0x8400
268 #define _VLV_PCS01_DW0_CH0		0x200
269 #define _VLV_PCS23_DW0_CH0		0x400
270 #define _VLV_PCS01_DW0_CH1		0x2600
271 #define _VLV_PCS23_DW0_CH1		0x2800
275 #define _VLV_PCS_DW1_CH0		0x8204
276 #define _VLV_PCS_DW1_CH1		0x8404
284 #define _VLV_PCS01_DW1_CH0		0x204
285 #define _VLV_PCS23_DW1_CH0		0x404
286 #define _VLV_PCS01_DW1_CH1		0x2604
287 #define _VLV_PCS23_DW1_CH1		0x2804
291 #define _VLV_PCS_DW8_CH0		0x8220
292 #define _VLV_PCS_DW8_CH1		0x8420
297 #define _VLV_PCS01_DW8_CH0		0x0220
298 #define _VLV_PCS23_DW8_CH0		0x0420
299 #define _VLV_PCS01_DW8_CH1		0x2620
300 #define _VLV_PCS23_DW8_CH1		0x2820
304 #define _VLV_PCS_DW9_CH0		0x8224
305 #define _VLV_PCS_DW9_CH1		0x8424
306 #define   DPIO_PCS_TX2MARGIN_MASK	(0x7 << 13)
307 #define   DPIO_PCS_TX2MARGIN_000	(0 << 13)
309 #define   DPIO_PCS_TX1MARGIN_MASK	(0x7 << 10)
310 #define   DPIO_PCS_TX1MARGIN_000	(0 << 10)
314 #define _VLV_PCS01_DW9_CH0		0x224
315 #define _VLV_PCS23_DW9_CH0		0x424
316 #define _VLV_PCS01_DW9_CH1		0x2624
317 #define _VLV_PCS23_DW9_CH1		0x2824
321 #define _CHV_PCS_DW10_CH0		0x8228
322 #define _CHV_PCS_DW10_CH1		0x8428
325 #define   DPIO_PCS_TX2DEEMP_MASK	(0xf << 24)
326 #define   DPIO_PCS_TX2DEEMP_9P5		(0 << 24)
328 #define   DPIO_PCS_TX1DEEMP_MASK	(0xf << 16)
329 #define   DPIO_PCS_TX1DEEMP_9P5		(0 << 16)
333 #define _VLV_PCS01_DW10_CH0		0x0228
334 #define _VLV_PCS23_DW10_CH0		0x0428
335 #define _VLV_PCS01_DW10_CH1		0x2628
336 #define _VLV_PCS23_DW10_CH1		0x2828
340 #define _VLV_PCS_DW11_CH0		0x822c
341 #define _VLV_PCS_DW11_CH1		0x842c
345 #define   DPIO_RIGHT_TXFIFO_RST_MASTER	(1 << 0)
348 #define _VLV_PCS01_DW11_CH0		0x022c
349 #define _VLV_PCS23_DW11_CH0		0x042c
350 #define _VLV_PCS01_DW11_CH1		0x262c
351 #define _VLV_PCS23_DW11_CH1		0x282c
355 #define _VLV_PCS01_DW12_CH0		0x0230
356 #define _VLV_PCS23_DW12_CH0		0x0430
357 #define _VLV_PCS01_DW12_CH1		0x2630
358 #define _VLV_PCS23_DW12_CH1		0x2830
362 #define _VLV_PCS_DW12_CH0		0x8230
363 #define _VLV_PCS_DW12_CH1		0x8430
368 #define   DPIO_LANESTAGGER_STRAP(x)	((x) << 0)
371 #define _VLV_PCS_DW14_CH0		0x8238
372 #define _VLV_PCS_DW14_CH1		0x8438
375 #define _VLV_PCS_DW23_CH0		0x825c
376 #define _VLV_PCS_DW23_CH1		0x845c
379 #define _VLV_TX_DW2_CH0			0x8288
380 #define _VLV_TX_DW2_CH1			0x8488
382 #define   DPIO_SWING_MARGIN000_MASK	(0xff << DPIO_SWING_MARGIN000_SHIFT)
386 #define _VLV_TX_DW3_CH0			0x828c
387 #define _VLV_TX_DW3_CH1			0x848c
391 #define   DPIO_SWING_MARGIN101_MASK	(0xff << DPIO_SWING_MARGIN101_SHIFT)
394 #define _VLV_TX_DW4_CH0			0x8290
395 #define _VLV_TX_DW4_CH1			0x8490
397 #define   DPIO_SWING_DEEMPH9P5_MASK	(0xff << DPIO_SWING_DEEMPH9P5_SHIFT)
399 #define   DPIO_SWING_DEEMPH6P0_MASK	(0xff << DPIO_SWING_DEEMPH6P0_SHIFT)
402 #define _VLV_TX3_DW4_CH0		0x690
403 #define _VLV_TX3_DW4_CH1		0x2a90
406 #define _VLV_TX_DW5_CH0			0x8294
407 #define _VLV_TX_DW5_CH1			0x8494
411 #define _VLV_TX_DW11_CH0		0x82ac
412 #define _VLV_TX_DW11_CH1		0x84ac
415 #define _VLV_TX_DW14_CH0		0x82b8
416 #define _VLV_TX_DW14_CH1		0x84b8
420 #define _CHV_PLL_DW0_CH0		0x8000
421 #define _CHV_PLL_DW0_CH1		0x8180
424 #define _CHV_PLL_DW1_CH0		0x8004
425 #define _CHV_PLL_DW1_CH1		0x8184
427 #define   DPIO_CHV_M1_DIV_BY_2		(0 << 0)
430 #define _CHV_PLL_DW2_CH0		0x8008
431 #define _CHV_PLL_DW2_CH1		0x8188
434 #define _CHV_PLL_DW3_CH0		0x800c
435 #define _CHV_PLL_DW3_CH1		0x818c
437 #define  DPIO_CHV_FIRST_MOD		(0 << 8)
439 #define  DPIO_CHV_FEEDFWD_GAIN_SHIFT	0
440 #define  DPIO_CHV_FEEDFWD_GAIN_MASK		(0xF << 0)
443 #define _CHV_PLL_DW6_CH0		0x8018
444 #define _CHV_PLL_DW6_CH1		0x8198
447 #define   DPIO_CHV_PROP_COEFF_SHIFT	0
450 #define _CHV_PLL_DW8_CH0		0x8020
451 #define _CHV_PLL_DW8_CH1		0x81A0
452 #define   DPIO_CHV_TDC_TARGET_CNT_SHIFT 0
453 #define   DPIO_CHV_TDC_TARGET_CNT_MASK  (0x3FF << 0)
456 #define _CHV_PLL_DW9_CH0		0x8024
457 #define _CHV_PLL_DW9_CH1		0x81A4
460 #define  DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE	1 /* 1: coarse & 0 : fine  */
463 #define _CHV_CMN_DW0_CH0               0x8100
467 #define   DPIO_ANYDL_POWERDOWN			(1 << 0)
469 #define _CHV_CMN_DW5_CH0               0x8114
470 #define   CHV_BUFRIGHTENA1_DISABLE	(0 << 20)
474 #define   CHV_BUFLEFTENA1_DISABLE	(0 << 22)
479 #define _CHV_CMN_DW13_CH0		0x8134
480 #define _CHV_CMN_DW0_CH1		0x8080
486 #define   DPIO_PLL_LOCK			(1 << 0)
489 #define _CHV_CMN_DW14_CH0		0x8138
490 #define _CHV_CMN_DW1_CH1		0x8084
493 #define   CHV_BUFLEFTENA2_DISABLE	(0 << 17) /* CL2 DW1 only */
497 #define   CHV_BUFRIGHTENA2_DISABLE	(0 << 19) /* CL2 DW1 only */
503 #define _CHV_CMN_DW19_CH0		0x814c
504 #define _CHV_CMN_DW6_CH1		0x8098
512 #define CHV_CMN_DW28			0x8170
515 #define   DPIO_SUS_CLK_CONFIG_ON		(0 << 0)
516 #define   DPIO_SUS_CLK_CONFIG_CLKREQ		(1 << 0)
517 #define   DPIO_SUS_CLK_CONFIG_GATE		(2 << 0)
518 #define   DPIO_SUS_CLK_CONFIG_GATE_CLKREQ	(3 << 0)
520 #define CHV_CMN_DW30			0x8178
524 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \
525 					(lane) * 0x200 + (offset))
527 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80)
528 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84)
529 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88)
530 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c)
531 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90)
532 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94)
533 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98)
534 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c)
535 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0)
536 #define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4)
537 #define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8)
538 #define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac)
540 #define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8)
544 #define _BXT_PHY0_BASE			0x6C000
545 #define _BXT_PHY1_BASE			0x162000
546 #define _BXT_PHY2_BASE			0x163000
561 #define BXT_P_CR_GT_DISP_PWRON		_MMIO(0x138090)
564 #define _BXT_PHY_CTL_DDI_A		0x64C00
565 #define _BXT_PHY_CTL_DDI_B		0x64C10
566 #define _BXT_PHY_CTL_DDI_C		0x64C20
573 #define _PHY_CTL_FAMILY_DDI		0x64C90
574 #define _PHY_CTL_FAMILY_EDP		0x64C80
575 #define _PHY_CTL_FAMILY_DDI_C		0x64CA0
583 #define _PORT_PLL_A			0x46074
584 #define _PORT_PLL_B			0x46078
585 #define _PORT_PLL_C			0x4607c
593 #define _PORT_PLL_EBB_0_A		0x162034
594 #define _PORT_PLL_EBB_0_B		0x6C034
595 #define _PORT_PLL_EBB_0_C		0x6C340
604 #define _PORT_PLL_EBB_4_A		0x162038
605 #define _PORT_PLL_EBB_4_B		0x6C038
606 #define _PORT_PLL_EBB_4_C		0x6C344
613 #define _PORT_PLL_0_A			0x162100
614 #define _PORT_PLL_0_B			0x6C100
615 #define _PORT_PLL_0_C			0x6C380
617 #define   PORT_PLL_M2_INT_MASK		REG_GENMASK(7, 0)
623 #define   PORT_PLL_M2_FRAC_MASK		REG_GENMASK(21, 0)
632 #define   PORT_PLL_PROP_COEFF_MASK	REG_GENMASK(3, 0)
635 #define   PORT_PLL_TARGET_CNT_MASK	REG_GENMASK(9, 0)
651 #define _PORT_CL1CM_DW0_A		0x162000
652 #define _PORT_CL1CM_DW0_BC		0x6C000
657 #define _PORT_CL1CM_DW9_A		0x162024
658 #define _PORT_CL1CM_DW9_BC		0x6C024
660 #define   IREF0RC_OFFSET_MASK		(0xFF << IREF0RC_OFFSET_SHIFT)
663 #define _PORT_CL1CM_DW10_A		0x162028
664 #define _PORT_CL1CM_DW10_BC		0x6C028
666 #define   IREF1RC_OFFSET_MASK		(0xFF << IREF1RC_OFFSET_SHIFT)
669 #define _PORT_CL1CM_DW28_A		0x162070
670 #define _PORT_CL1CM_DW28_BC		0x6C070
673 #define   SUS_CLK_CONFIG		0x3
676 #define _PORT_CL1CM_DW30_A		0x162078
677 #define _PORT_CL1CM_DW30_BC		0x6C078
684 #define _PORT_CL2CM_DW6_A		0x162358
685 #define _PORT_CL2CM_DW6_BC		0x6C358
690 #define _PORT_REF_DW3_A			0x16218C
691 #define _PORT_REF_DW3_BC		0x6C18C
695 #define _PORT_REF_DW6_A			0x162198
696 #define _PORT_REF_DW6_BC		0x6C198
698 #define   GRC_CODE_MASK			(0xFF << GRC_CODE_SHIFT)
700 #define   GRC_CODE_FAST_MASK		(0xFF << GRC_CODE_FAST_SHIFT)
702 #define   GRC_CODE_SLOW_MASK		(0xFF << GRC_CODE_SLOW_SHIFT)
703 #define   GRC_CODE_NOM_MASK		0xFF
706 #define _PORT_REF_DW8_A			0x1621A0
707 #define _PORT_REF_DW8_BC		0x6C1A0
713 #define _PORT_PCS_DW10_LN01_A		0x162428
714 #define _PORT_PCS_DW10_LN01_B		0x6C428
715 #define _PORT_PCS_DW10_LN01_C		0x6C828
716 #define _PORT_PCS_DW10_GRP_A		0x162C28
717 #define _PORT_PCS_DW10_GRP_B		0x6CC28
718 #define _PORT_PCS_DW10_GRP_C		0x6CE28
729 #define _PORT_PCS_DW12_LN01_A		0x162430
730 #define _PORT_PCS_DW12_LN01_B		0x6C430
731 #define _PORT_PCS_DW12_LN01_C		0x6C830
732 #define _PORT_PCS_DW12_LN23_A		0x162630
733 #define _PORT_PCS_DW12_LN23_B		0x6C630
734 #define _PORT_PCS_DW12_LN23_C		0x6CA30
735 #define _PORT_PCS_DW12_GRP_A		0x162c30
736 #define _PORT_PCS_DW12_GRP_B		0x6CC30
737 #define _PORT_PCS_DW12_GRP_C		0x6CE30
739 #define   LANE_STAGGER_MASK		0x1F
751 #define _BXT_LANE_OFFSET(lane)           (((lane) >> 1) * 0x200 +	\
752 					  ((lane) & 1) * 0x80)
754 #define _PORT_TX_DW2_LN0_A		0x162508
755 #define _PORT_TX_DW2_LN0_B		0x6C508
756 #define _PORT_TX_DW2_LN0_C		0x6C908
757 #define _PORT_TX_DW2_GRP_A		0x162D08
758 #define _PORT_TX_DW2_GRP_B		0x6CD08
759 #define _PORT_TX_DW2_GRP_C		0x6CF08
767 #define   MARGIN_000			(0xFF << MARGIN_000_SHIFT)
769 #define   UNIQ_TRANS_SCALE		(0xFF << UNIQ_TRANS_SCALE_SHIFT)
771 #define _PORT_TX_DW3_LN0_A		0x16250C
772 #define _PORT_TX_DW3_LN0_B		0x6C50C
773 #define _PORT_TX_DW3_LN0_C		0x6C90C
774 #define _PORT_TX_DW3_GRP_A		0x162D0C
775 #define _PORT_TX_DW3_GRP_B		0x6CD0C
776 #define _PORT_TX_DW3_GRP_C		0x6CF0C
786 #define _PORT_TX_DW4_LN0_A		0x162510
787 #define _PORT_TX_DW4_LN0_B		0x6C510
788 #define _PORT_TX_DW4_LN0_C		0x6C910
789 #define _PORT_TX_DW4_GRP_A		0x162D10
790 #define _PORT_TX_DW4_GRP_B		0x6CD10
791 #define _PORT_TX_DW4_GRP_C		0x6CF10
799 #define   DE_EMPHASIS			(0xFF << DEEMPH_SHIFT)
801 #define _PORT_TX_DW5_LN0_A		0x162514
802 #define _PORT_TX_DW5_LN0_B		0x6C514
803 #define _PORT_TX_DW5_LN0_C		0x6C914
804 #define _PORT_TX_DW5_GRP_A		0x162D14
805 #define _PORT_TX_DW5_GRP_B		0x6CD14
806 #define _PORT_TX_DW5_GRP_C		0x6CF14
816 #define _PORT_TX_DW14_LN0_A		0x162538
817 #define _PORT_TX_DW14_LN0_B		0x6C538
818 #define _PORT_TX_DW14_LN0_C		0x6C938
827 #define UAIMI_SPR1			_MMIO(0x4F074)
829 #define SKL_VCCIO_MASK			0x1
831 #define DISPIO_CR_TX_BMU_CR0		_MMIO(0x6C00C)
841  * [0-7]  @ 0x2000 gen2,gen3
842  * [8-15] @ 0x3000 945,g33,pnv
844  * [0-15] @ 0x3000 gen4,gen5
846  * [0-15] @ 0x100000 gen6,vlv,chv
847  * [0-31] @ 0x100000 gen7+
849 #define FENCE_REG(i)			_MMIO(0x2000 + (((i) & 8) << 9) + ((i) & 7) * 4)
850 #define   I830_FENCE_START_MASK		0x07f80000
854 #define   I830_FENCE_REG_VALID		(1 << 0)
859 #define   I915_FENCE_START_MASK		0x0ff00000
862 #define FENCE_REG_965_LO(i)		_MMIO(0x03000 + (i) * 8)
863 #define FENCE_REG_965_HI(i)		_MMIO(0x03000 + (i) * 8 + 4)
866 #define   I965_FENCE_REG_VALID		(1 << 0)
867 #define   I965_FENCE_MAX_PITCH_VAL	0x0400
869 #define FENCE_REG_GEN6_LO(i)		_MMIO(0x100000 + (i) * 8)
870 #define FENCE_REG_GEN6_HI(i)		_MMIO(0x100000 + (i) * 8 + 4)
872 #define   GEN7_FENCE_MAX_PITCH_VAL	0x0800
876 #define TILECTL				_MMIO(0x101000)
877 #define   TILECTL_SWZCTL			(1 << 0)
885 #define PGTBL_CTL	_MMIO(0x02020)
886 #define   PGTBL_ADDRESS_LO_MASK	0xfffff000 /* bits [31:12] */
887 #define   PGTBL_ADDRESS_HI_MASK	0x000000f0 /* bits [35:32] (gen4) */
888 #define PGTBL_ER	_MMIO(0x02024)
889 #define PRB0_BASE	(0x2030 - 0x30)
890 #define PRB1_BASE	(0x2040 - 0x30) /* 830,gen3 */
891 #define PRB2_BASE	(0x2050 - 0x30) /* gen3 */
892 #define SRB0_BASE	(0x2100 - 0x30) /* gen2 */
893 #define SRB1_BASE	(0x2110 - 0x30) /* gen2 */
894 #define SRB2_BASE	(0x2120 - 0x30) /* 830 */
895 #define SRB3_BASE	(0x2130 - 0x30) /* 830 */
896 #define RENDER_RING_BASE	0x02000
897 #define BSD_RING_BASE		0x04000
898 #define GEN6_BSD_RING_BASE	0x12000
899 #define GEN8_BSD2_RING_BASE	0x1c000
900 #define GEN11_BSD_RING_BASE	0x1c0000
901 #define GEN11_BSD2_RING_BASE	0x1c4000
902 #define GEN11_BSD3_RING_BASE	0x1d0000
903 #define GEN11_BSD4_RING_BASE	0x1d4000
904 #define XEHP_BSD5_RING_BASE	0x1e0000
905 #define XEHP_BSD6_RING_BASE	0x1e4000
906 #define XEHP_BSD7_RING_BASE	0x1f0000
907 #define XEHP_BSD8_RING_BASE	0x1f4000
908 #define VEBOX_RING_BASE		0x1a000
909 #define GEN11_VEBOX_RING_BASE		0x1c8000
910 #define GEN11_VEBOX2_RING_BASE		0x1d8000
911 #define XEHP_VEBOX3_RING_BASE		0x1e8000
912 #define XEHP_VEBOX4_RING_BASE		0x1f8000
913 #define MTL_GSC_RING_BASE		0x11a000
914 #define GEN12_COMPUTE0_RING_BASE	0x1a000
915 #define GEN12_COMPUTE1_RING_BASE	0x1c000
916 #define GEN12_COMPUTE2_RING_BASE	0x1e000
917 #define GEN12_COMPUTE3_RING_BASE	0x26000
918 #define BLT_RING_BASE		0x22000
919 #define XEHPC_BCS1_RING_BASE	0x3e0000
920 #define XEHPC_BCS2_RING_BASE	0x3e2000
921 #define XEHPC_BCS3_RING_BASE	0x3e4000
922 #define XEHPC_BCS4_RING_BASE	0x3e6000
923 #define XEHPC_BCS5_RING_BASE	0x3e8000
924 #define XEHPC_BCS6_RING_BASE	0x3ea000
925 #define XEHPC_BCS7_RING_BASE	0x3ec000
926 #define XEHPC_BCS8_RING_BASE	0x3ee000
927 #define DG1_GSC_HECI1_BASE	0x00258000
928 #define DG1_GSC_HECI2_BASE	0x00259000
929 #define DG2_GSC_HECI1_BASE	0x00373000
930 #define DG2_GSC_HECI2_BASE	0x00374000
931 #define MTL_GSC_HECI1_BASE	0x00116000
932 #define MTL_GSC_HECI2_BASE	0x00117000
934 #define HECI_H_CSR(base)	_MMIO((base) + 0x4)
935 #define   HECI_H_CSR_IE		REG_BIT(0)
941 #define HECI_H_GS1(base)	_MMIO((base) + 0xc4c)
942 #define   HECI_H_GS1_ER_PREP	REG_BIT(0)
948 #define HECI_FWSTS1				0xc40
949 #define   HECI1_FWSTS1_CURRENT_STATE			REG_GENMASK(3, 0)
950 #define   HECI1_FWSTS1_CURRENT_STATE_RESET		0
953 #define HECI_FWSTS2				0xc48
954 #define HECI_FWSTS3				0xc60
955 #define HECI_FWSTS4				0xc64
956 #define HECI_FWSTS5				0xc68
958 #define HECI_FWSTS6				0xc6c
960 /* the FWSTS regs are 1-based, so we use -base for index 0 to get an invalid reg */
969 #define HSW_GTT_CACHE_EN	_MMIO(0x4024)
970 #define   GTT_CACHE_EN_ALL	0xF0007FFF
971 #define GEN7_WR_WATERMARK	_MMIO(0x4028)
972 #define GEN7_GFX_PRIO_CTRL	_MMIO(0x402C)
973 #define ARB_MODE		_MMIO(0x4030)
976 #define GEN7_GFX_PEND_TLB0	_MMIO(0x4034)
977 #define GEN7_GFX_PEND_TLB1	_MMIO(0x4038)
979 #define GEN7_LRA_LIMITS(i)	_MMIO(0x403C + (i) * 4)
981 #define GEN7_MEDIA_MAX_REQ_COUNT	_MMIO(0x4070)
982 #define GEN7_GFX_MAX_REQ_COUNT		_MMIO(0x4074)
984 #define GEN7_ERR_INT	_MMIO(0x44040)
993 #define   ERR_INT_FIFO_UNDERRUN_A	(1 << 0)
996 #define FPGA_DBG		_MMIO(0x42300)
999 #define CLAIM_ER		_MMIO(VLV_DISPLAY_BASE + 0x2028)
1002 #define   CLAIM_ER_CTR_MASK	REG_GENMASK(15, 0)
1004 #define DERRMR		_MMIO(0x44050)
1006 #define   DERRMR_PIPEA_SCANLINE		(1 << 0)
1023 #define VLV_GU_CTL0	_MMIO(VLV_DISPLAY_BASE + 0x2030)
1024 #define VLV_GU_CTL1	_MMIO(VLV_DISPLAY_BASE + 0x2034)
1025 #define SCPD0		_MMIO(0x209c) /* 915+ only */
1028 #define GEN2_IER	_MMIO(0x20a0)
1029 #define GEN2_IIR	_MMIO(0x20a4)
1030 #define GEN2_IMR	_MMIO(0x20a8)
1031 #define GEN2_ISR	_MMIO(0x20ac)
1032 #define VLV_GUNIT_CLOCK_GATE	_MMIO(VLV_DISPLAY_BASE + 0x2060)
1035 #define VLV_GUNIT_CLOCK_GATE2	_MMIO(VLV_DISPLAY_BASE + 0x2064)
1036 #define VLV_IIR_RW	_MMIO(VLV_DISPLAY_BASE + 0x2084)
1037 #define VLV_IER		_MMIO(VLV_DISPLAY_BASE + 0x20a0)
1038 #define VLV_IIR		_MMIO(VLV_DISPLAY_BASE + 0x20a4)
1039 #define VLV_IMR		_MMIO(VLV_DISPLAY_BASE + 0x20a8)
1040 #define VLV_ISR		_MMIO(VLV_DISPLAY_BASE + 0x20ac)
1041 #define VLV_PCBR	_MMIO(VLV_DISPLAY_BASE + 0x2120)
1045 #define EIR		_MMIO(0x20b0)
1046 #define EMR		_MMIO(0x20b4)
1047 #define ESR		_MMIO(0x20b8)
1053 #define   I915_ERROR_INSTRUCTION			(1 << 0)
1054 #define INSTPM	        _MMIO(0x20c0)
1062 #define MEM_MODE	_MMIO(0x20cc)
1066 #define FW_BLC		_MMIO(0x20d8)
1067 #define FW_BLC2		_MMIO(0x20dc)
1068 #define FW_BLC_SELF	_MMIO(0x20e0) /* 915+ only */
1072 #define MM_BURST_LENGTH     0x00700000
1073 #define MM_FIFO_WATERMARK   0x0001F000
1074 #define LM_BURST_LENGTH     0x00000700
1075 #define LM_FIFO_WATERMARK   0x0000001F
1076 #define MI_ARB_STATE	_MMIO(0x20e4) /* 915+ only */
1078 #define _MBUS_ABOX0_CTL			0x45038
1079 #define _MBUS_ABOX1_CTL			0x45048
1080 #define _MBUS_ABOX2_CTL			0x4504C
1088 #define MBUS_ABOX_B_CREDIT_MASK		(0xF << 16)
1090 #define MBUS_ABOX_BT_CREDIT_POOL2_MASK	(0x1F << 8)
1092 #define MBUS_ABOX_BT_CREDIT_POOL1_MASK	(0x1F << 0)
1093 #define MBUS_ABOX_BT_CREDIT_POOL1(x)	((x) << 0)
1110 #define   MI_ARB_BLOCK_GRANT_8			(0 << 12)	/* for 3 display planes */
1137 #define   MI_ARB_TIME_SLICE_1			(0 << 5)
1147 #define   MI_ARB_LOW_PRIORITY_GRACE_4KB		(0 << 4)	/* default */
1154 #define   MI_ARB_DISPLAY_PRIORITY_A_B		(0 << 0)	/* display A > display B */
1155 #define   MI_ARB_DISPLAY_PRIORITY_B_A		(1 << 0)	/* display B > display A */
1157 #define MI_STATE	_MMIO(0x20e4) /* gen2 only */
1159 #define   MI_AGPBUSY_830_MODE			(1 << 0) /* 85x only */
1185 #define GT_RENDER_USER_INTERRUPT		(1 <<  0)
1192 	 (IS_HASWELL(dev_priv) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1230 #define I915_ASLE_INTERRUPT				(1 << 0)
1233 #define I915_HDMI_LPE_AUDIO_BASE	(VLV_DISPLAY_BASE + 0x65000)
1234 #define I915_HDMI_LPE_AUDIO_SIZE	0x1000
1237 #define VLV_AUD_CHICKEN_BIT_REG		_MMIO(VLV_DISPLAY_BASE + 0x62F38)
1238 #define VLV_CHICKEN_BIT_DBG_ENABLE	(1 << 0)
1240 #define _VLV_AUD_PORT_EN_B_DBG		(VLV_DISPLAY_BASE + 0x62F20)
1241 #define _VLV_AUD_PORT_EN_C_DBG		(VLV_DISPLAY_BASE + 0x62F30)
1242 #define _VLV_AUD_PORT_EN_D_DBG		(VLV_DISPLAY_BASE + 0x62F34)
1249 #define GEN6_BSD_RNCID			_MMIO(0x12198)
1251 #define GEN7_FF_THREAD_MODE		_MMIO(0x20a0)
1252 #define   GEN7_FF_SCHED_MASK		0x0077070
1255 #define   GEN7_FF_TS_SCHED_HS1		(0x5 << 16)
1256 #define   GEN7_FF_TS_SCHED_HS0		(0x3 << 16)
1257 #define   GEN7_FF_TS_SCHED_LOAD_BALANCE	(0x1 << 16)
1258 #define   GEN7_FF_TS_SCHED_HW		(0x0 << 16) /* Default */
1260 #define   GEN7_FF_VS_SCHED_HS1		(0x5 << 12)
1261 #define   GEN7_FF_VS_SCHED_HS0		(0x3 << 12)
1262 #define   GEN7_FF_VS_SCHED_LOAD_BALANCE	(0x1 << 12) /* Default */
1263 #define   GEN7_FF_VS_SCHED_HW		(0x0 << 12)
1264 #define   GEN7_FF_DS_SCHED_HS1		(0x5 << 4)
1265 #define   GEN7_FF_DS_SCHED_HS0		(0x3 << 4)
1266 #define   GEN7_FF_DS_SCHED_LOAD_BALANCE	(0x1 << 4)  /* Default */
1267 #define   GEN7_FF_DS_SCHED_HW		(0x0 << 4)
1273 #define FBC_CFB_BASE		_MMIO(0x3200) /* 4k page aligned */
1274 #define FBC_LL_BASE		_MMIO(0x3204) /* 4k page aligned */
1275 #define FBC_CONTROL		_MMIO(0x3208)
1285 #define   FBC_CTL_FENCENO_MASK		REG_GENMASK(3, 0)
1287 #define FBC_COMMAND		_MMIO(0x320c)
1288 #define   FBC_CMD_COMPRESS		REG_BIT(0)
1289 #define FBC_STATUS		_MMIO(0x3210)
1293 #define   FBC_STAT_CURRENT_LINE_MASK	REG_GENMASK(10, 0)
1294 #define FBC_CONTROL2		_MMIO(0x3214) /* i965gm only */
1297 #define   FBC_CTL_IDLE_IMM		REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
1302 #define   FBC_CTL_PLANE_MASK		REG_GENMASK(1, 0)
1304 #define FBC_FENCE_OFF		_MMIO(0x3218)  /* i965gm only, BSpec typo has 321Bh */
1305 #define FBC_MOD_NUM		_MMIO(0x3220)  /* i965gm only */
1307 #define   FBC_MOD_NUM_VALID		REG_BIT(0)
1308 #define FBC_TAG(i)		_MMIO(0x3300 + (i) * 4) /* 49 reisters */
1309 #define   FBC_TAG_MASK			REG_GENMASK(1, 0) /* 16 tags per register */
1310 #define   FBC_TAG_MODIFIED		REG_FIELD_PREP(FBC_TAG_MASK, 0)
1318 #define DPFC_CB_BASE			_MMIO(0x3200)
1319 #define ILK_DPFC_CB_BASE(fbc_id)	_MMIO_PIPE((fbc_id), 0x43200, 0x43240)
1320 #define DPFC_CONTROL			_MMIO(0x3208)
1321 #define ILK_DPFC_CONTROL(fbc_id)	_MMIO_PIPE((fbc_id), 0x43208, 0x43248)
1334 #define   DPFC_CTL_LIMIT_1X			REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
1337 #define   DPFC_CTL_FENCENO_MASK			REG_GENMASK(3, 0)
1339 #define DPFC_RECOMP_CTL			_MMIO(0x320c)
1340 #define ILK_DPFC_RECOMP_CTL(fbc_id)	_MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
1343 #define   DPFC_RECOMP_TIMER_COUNT_MASK		REG_GENMASK(5, 0)
1344 #define DPFC_STATUS			_MMIO(0x3210)
1345 #define ILK_DPFC_STATUS(fbc_id)		_MMIO_PIPE((fbc_id), 0x43210, 0x43250)
1347 #define   DPFC_COMP_SEG_MASK			REG_GENMASK(10, 0)
1348 #define DPFC_STATUS2			_MMIO(0x3214)
1349 #define ILK_DPFC_STATUS2(fbc_id)	_MMIO_PIPE((fbc_id), 0x43214, 0x43254)
1350 #define   DPFC_COMP_SEG_MASK_IVB		REG_GENMASK(11, 0)
1351 #define DPFC_FENCE_YOFF			_MMIO(0x3218)
1352 #define ILK_DPFC_FENCE_YOFF(fbc_id)	_MMIO_PIPE((fbc_id), 0x43218, 0x43258)
1353 #define DPFC_CHICKEN			_MMIO(0x3224)
1354 #define ILK_DPFC_CHICKEN(fbc_id)	_MMIO_PIPE((fbc_id), 0x43224, 0x43264)
1361 #define GLK_FBC_STRIDE(fbc_id)	_MMIO_PIPE((fbc_id), 0x43228, 0x43268)
1363 #define   FBC_STRIDE_MASK	REG_GENMASK(14, 0)
1366 #define ILK_FBC_RT_BASE		_MMIO(0x2128)
1367 #define   ILK_FBC_RT_VALID	REG_BIT(0)
1370 #define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)
1375 #define   IVB_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)
1380 #define   IVB_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)
1391 #define SNB_DPFC_CTL_SA		_MMIO(0x100100)
1393 #define   SNB_DPFC_FENCENO_MASK		REG_GENMASK(4, 0)
1395 #define SNB_DPFC_CPU_FENCE_OFFSET	_MMIO(0x100104)
1398 #define IVB_FBC_RT_BASE			_MMIO(0x7020)
1399 #define IVB_FBC_RT_BASE_UPPER		_MMIO(0x7024)
1401 #define IPS_CTL		_MMIO(0x43408)
1405 #define MSG_FBC_REND_STATE(fbc_id)	_MMIO_PIPE((fbc_id), 0x50380, 0x50384)
1412 #define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014)
1413 #define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018)
1414 #define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030)
1417 #define VGA0	_MMIO(0x6000)
1418 #define VGA1	_MMIO(0x6004)
1419 #define VGA_PD	_MMIO(0x6010)
1422 #define   VGA0_PD_P1_SHIFT	0
1423 #define   VGA0_PD_P1_MASK	(0x1f << 0)
1427 #define   VGA1_PD_P1_MASK	(0x1f << 8)
1438 #define   DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1440 #define   DPLLB_LVDS_P2_CLOCK_DIV_14	(0 << 24) /* i915 */
1442 #define   DPLL_P2_CLOCK_DIV_MASK	0x03000000 /* i915 */
1443 #define   DPLL_FPA01_P1_POST_DIV_MASK	0x00ff0000 /* i915 */
1444 #define   DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW	0x00ff8000 /* Pineview */
1449 #define   DPLL_PORTC_READY_MASK		(0xf << 4)
1450 #define   DPLL_PORTB_READY_MASK		(0xf)
1452 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830	0x001f0000
1455 #define DPIO_PHY_STATUS			_MMIO(VLV_DISPLAY_BASE + 0x6240)
1456 #define   DPLL_PORTD_READY_MASK		(0xf)
1457 #define DISPLAY_PHY_CONTROL _MMIO(VLV_DISPLAY_BASE + 0x60100)
1459 #define   PHY_LDO_DELAY_0NS			0x0
1460 #define   PHY_LDO_DELAY_200NS			0x1
1461 #define   PHY_LDO_DELAY_600NS			0x2
1464 #define   PHY_CH_SU_PSR				0x1
1465 #define   PHY_CH_DEEP_PSR			0x7
1468 #define DISPLAY_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x60104)
1477 #define   DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS	0x003f0000
1483 #define   PLL_REF_INPUT_DREFCLK		(0 << 13)
1493 # define DPLL_FPA1_P1_POST_DIV_SHIFT            0
1494 # define DPLL_FPA1_P1_POST_DIV_MASK             0xff
1502 #define   PLL_LOAD_PULSE_PHASE_MASK		(0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1507 #define   SDVO_MULTIPLIER_MASK			0x000000ff
1509 #define   SDVO_MULTIPLIER_SHIFT_VGA		0
1511 #define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c)
1512 #define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020)
1513 #define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c)
1521 #define   DPLL_MD_UDI_DIVIDER_MASK		0x3f000000
1524 #define   DPLL_MD_VGA_UDI_DIVIDER_MASK		0x003f0000
1543 #define   DPLL_MD_UDI_MULTIPLIER_MASK		0x00003f00
1550 #define   DPLL_MD_VGA_UDI_MULTIPLIER_MASK	0x0000003f
1551 #define   DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT	0
1553 #define RAWCLK_FREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6024)
1555 #define _FPA0	0x6040
1556 #define _FPA1	0x6044
1557 #define _FPB0	0x6048
1558 #define _FPB1	0x604c
1561 #define   FP_N_DIV_MASK		0x003f0000
1562 #define   FP_N_PINEVIEW_DIV_MASK	0x00ff0000
1564 #define   FP_M1_DIV_MASK	0x00003f00
1566 #define   FP_M2_DIV_MASK	0x0000003f
1567 #define   FP_M2_PINEVIEW_DIV_MASK	0x000000ff
1568 #define   FP_M2_DIV_SHIFT		 0
1569 #define DPLL_TEST	_MMIO(0x606c)
1570 #define   DPLLB_TEST_SDVO_DIV_1		(0 << 22)
1579 #define   DPLLA_INPUT_BUFFER_ENABLE	(1 << 0)
1580 #define D_STATE		_MMIO(0x6104)
1584 #define  DSTATE_DOT_CLOCK_GATING		(1 << 0)
1585 #define DSPCLK_GATE_D(__i915)		_MMIO(DISPLAY_MMIO_BASE(__i915) + 0x6200)
1622 # define ZVUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 830 */
1623 # define OVLUNIT_CLOCK_GATE_DISABLE		(1 << 0) /* 845,865 */
1625 #define RENCLK_GATE_D1		_MMIO(0x6204)
1641 # define SV_CLOCK_GATE_DISABLE			(1 << 0)
1658 # define I915_BY_CLOCK_GATE_DISABLE		(1 << 0)
1687 # define I965_DM_CLOCK_GATE_DISABLE		(1 << 0)
1689 #define RENCLK_GATE_D2		_MMIO(0x6208)
1694 #define VDECCLK_GATE_D		_MMIO(0x620C)		/* g4x only */
1697 #define RAMCLK_GATE_D		_MMIO(0x6210)		/* CRL only */
1698 #define DEUC			_MMIO(0x6214)          /* CRL only */
1700 #define FW_BLC_SELF_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6500)
1703 #define MI_ARB_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6504)
1705 #define CZCLK_CDCLK_FREQ_RATIO	_MMIO(VLV_DISPLAY_BASE + 0x6508)
1707 #define   CDCLK_FREQ_MASK	(0x1f << CDCLK_FREQ_SHIFT)
1708 #define   CZCLK_FREQ_MASK	0xf
1710 #define GCI_CONTROL		_MMIO(VLV_DISPLAY_BASE + 0x650C)
1717 #define GMBUSFREQ_VLV		_MMIO(VLV_DISPLAY_BASE + 0x6510)
1722 #define _PALETTE_A		0xa000
1723 #define _PALETTE_B		0xa800
1724 #define _CHV_PALETTE_C		0xc000
1728 #define   PALETTE_BLUE_MASK		REG_GENMASK(7, 0)
1732 #define   PALETTE_10BIT_BLUE_LDW_MASK	REG_GENMASK(7, 0)
1742 #define   PALETTE_10BIT_BLUE_UDW_MASK	REG_GENMASK(1, 0)
1749 #define PEG_BAND_GAP_DATA	_MMIO(0x14d68)
1751 #define BXT_RP_STATE_CAP        _MMIO(0x138170)
1752 #define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)
1753 #define XEHPSDV_RP_STATE_CAP	_MMIO(0x250014)
1754 #define PVC_RP_STATE_CAP	_MMIO(0x281014)
1756 #define MTL_RP_STATE_CAP	_MMIO(0x138000)
1757 #define MTL_MEDIAP_STATE_CAP	_MMIO(0x138020)
1758 #define   MTL_RP0_CAP_MASK	REG_GENMASK(8, 0)
1761 #define MTL_GT_RPE_FREQUENCY	_MMIO(0x13800c)
1762 #define MTL_MPE_FREQUENCY	_MMIO(0x13802c)
1763 #define   MTL_RPE_MASK		REG_GENMASK(8, 0)
1765 #define GT0_PERF_LIMIT_REASONS		_MMIO(0x1381a8)
1766 #define   GT0_PERF_LIMIT_REASONS_MASK	0xde3
1767 #define   PROCHOT_MASK			REG_BIT(0)
1776 #define MTL_MEDIA_PERF_LIMIT_REASONS	_MMIO(0x138030)
1778 #define CHV_CLK_CTL1			_MMIO(0x101100)
1779 #define VLV_CLK_CTL2			_MMIO(0x101104)
1786 #define OVADD			_MMIO(0x30000)
1787 #define DOVSTA			_MMIO(0x30008)
1788 #define OC_BUF			(0x3 << 20)
1789 #define OGAMC5			_MMIO(0x30010)
1790 #define OGAMC4			_MMIO(0x30014)
1791 #define OGAMC3			_MMIO(0x30018)
1792 #define OGAMC2			_MMIO(0x3001c)
1793 #define OGAMC1			_MMIO(0x30020)
1794 #define OGAMC0			_MMIO(0x30024)
1799 #define GEN9_CLKGATE_DIS_0		_MMIO(0x46530)
1806 #define GEN9_CLKGATE_DIS_3		_MMIO(0x46538)
1810 #define GEN9_CLKGATE_DIS_4		_MMIO(0x4653C)
1813 #define GEN9_CLKGATE_DIS_5		_MMIO(0x46540)
1816 #define _CLKGATE_DIS_PSL_A		0x46520
1817 #define _CLKGATE_DIS_PSL_B		0x46524
1818 #define _CLKGATE_DIS_PSL_C		0x46528
1830 #define _CLKGATE_DIS_PSL_EXT_A		0x4654C
1831 #define _CLKGATE_DIS_PSL_EXT_B		0x46550
1838 #define _DDI_CLK_VALFREQ_A		0x64030
1839 #define _DDI_CLK_VALFREQ_B		0x64130
1847 #define _PIPE_CRC_CTL_A			0x60050
1851 #define   PIPE_CRC_SOURCE_PLANE_1_SKL	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0)
1861 #define   PIPE_CRC_SOURCE_PRIMARY_IVB	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0)
1866 #define   PIPE_CRC_SOURCE_PRIMARY_ILK	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0)
1874 #define   PIPE_CRC_SOURCE_PIPE_VLV	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0)
1883 #define   PIPE_CRC_SOURCE_PIPE_I9XX	REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0)
1895 #define _PIPE_CRC_RES_1_A_IVB		0x60064
1896 #define _PIPE_CRC_RES_2_A_IVB		0x60068
1897 #define _PIPE_CRC_RES_3_A_IVB		0x6006c
1898 #define _PIPE_CRC_RES_4_A_IVB		0x60070
1899 #define _PIPE_CRC_RES_5_A_IVB		0x60074
1901 #define _PIPE_CRC_RES_RED_A		0x60060
1902 #define _PIPE_CRC_RES_GREEN_A		0x60064
1903 #define _PIPE_CRC_RES_BLUE_A		0x60068
1904 #define _PIPE_CRC_RES_RES1_A_I915	0x6006c
1905 #define _PIPE_CRC_RES_RES2_A_G4X	0x60080
1908 #define _PIPE_CRC_RES_1_B_IVB		0x61064
1909 #define _PIPE_CRC_RES_2_B_IVB		0x61068
1910 #define _PIPE_CRC_RES_3_B_IVB		0x6106c
1911 #define _PIPE_CRC_RES_4_B_IVB		0x61070
1912 #define _PIPE_CRC_RES_5_B_IVB		0x61074
1928 #define _TRANS_HTOTAL_A		0x60000
1931 #define   HACTIVE_MASK			REG_GENMASK(15, 0)
1933 #define _TRANS_HBLANK_A		0x60004
1936 #define   HBLANK_START_MASK		REG_GENMASK(15, 0)
1938 #define _TRANS_HSYNC_A		0x60008
1941 #define   HSYNC_START_MASK		REG_GENMASK(15, 0)
1943 #define _TRANS_VTOTAL_A		0x6000c
1946 #define   VACTIVE_MASK			REG_GENMASK(15, 0)
1948 #define _TRANS_VBLANK_A		0x60010
1951 #define   VBLANK_START_MASK		REG_GENMASK(15, 0)
1953 #define _TRANS_VSYNC_A		0x60014
1956 #define   VSYNC_START_MASK		REG_GENMASK(15, 0)
1958 #define _TRANS_EXITLINE_A	0x60018
1959 #define _PIPEASRC		0x6001c
1962 #define   PIPESRC_HEIGHT_MASK	REG_GENMASK(15, 0)
1964 #define _BCLRPAT_A		0x60020
1965 #define _TRANS_VSYNCSHIFT_A	0x60028
1966 #define _TRANS_MULT_A		0x6002c
1969 #define _TRANS_HTOTAL_B		0x61000
1970 #define _TRANS_HBLANK_B		0x61004
1971 #define _TRANS_HSYNC_B		0x61008
1972 #define _TRANS_VTOTAL_B		0x6100c
1973 #define _TRANS_VBLANK_B		0x61010
1974 #define _TRANS_VSYNC_B		0x61014
1975 #define _PIPEBSRC		0x6101c
1976 #define _BCLRPAT_B		0x61020
1977 #define _TRANS_VSYNCSHIFT_B	0x61028
1978 #define _TRANS_MULT_B		0x6102c
1980 /* DSI 0 timing regs */
1981 #define _TRANS_HTOTAL_DSI0	0x6b000
1982 #define _TRANS_HSYNC_DSI0	0x6b008
1983 #define _TRANS_VTOTAL_DSI0	0x6b00c
1984 #define _TRANS_VSYNC_DSI0	0x6b014
1985 #define _TRANS_VSYNCSHIFT_DSI0	0x6b028
1988 #define _TRANS_HTOTAL_DSI1	0x6b800
1989 #define _TRANS_HSYNC_DSI1	0x6b808
1990 #define _TRANS_VTOTAL_DSI1	0x6b80c
1991 #define _TRANS_VSYNC_DSI1	0x6b814
1992 #define _TRANS_VSYNCSHIFT_DSI1	0x6b828
2006 #define _TRANS_VRR_CTL_A		0x60420
2007 #define _TRANS_VRR_CTL_B		0x61420
2008 #define _TRANS_VRR_CTL_C		0x62420
2009 #define _TRANS_VRR_CTL_D		0x63420
2016 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
2017 #define	  XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
2020 #define _TRANS_VRR_VMAX_A		0x60424
2021 #define _TRANS_VRR_VMAX_B		0x61424
2022 #define _TRANS_VRR_VMAX_C		0x62424
2023 #define _TRANS_VRR_VMAX_D		0x63424
2025 #define   VRR_VMAX_MASK			REG_GENMASK(19, 0)
2027 #define _TRANS_VRR_VMIN_A		0x60434
2028 #define _TRANS_VRR_VMIN_B		0x61434
2029 #define _TRANS_VRR_VMIN_C		0x62434
2030 #define _TRANS_VRR_VMIN_D		0x63434
2032 #define   VRR_VMIN_MASK			REG_GENMASK(15, 0)
2034 #define _TRANS_VRR_VMAXSHIFT_A		0x60428
2035 #define _TRANS_VRR_VMAXSHIFT_B		0x61428
2036 #define _TRANS_VRR_VMAXSHIFT_C		0x62428
2037 #define _TRANS_VRR_VMAXSHIFT_D		0x63428
2042 #define   VRR_VMAXSHIFT_INC_MASK	REG_GENMASK(12, 0)
2044 #define _TRANS_VRR_STATUS_A		0x6042C
2045 #define _TRANS_VRR_STATUS_B		0x6142C
2046 #define _TRANS_VRR_STATUS_C		0x6242C
2047 #define _TRANS_VRR_STATUS_D		0x6342C
2056 #define   STATUS_FSM_IDLE		REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
2064 #define _TRANS_VRR_VTOTAL_PREV_A	0x60480
2065 #define _TRANS_VRR_VTOTAL_PREV_B	0x61480
2066 #define _TRANS_VRR_VTOTAL_PREV_C	0x62480
2067 #define _TRANS_VRR_VTOTAL_PREV_D	0x63480
2073 #define   VRR_VTOTAL_PREV_FRAME_MASK	REG_GENMASK(19, 0)
2075 #define _TRANS_VRR_FLIPLINE_A		0x60438
2076 #define _TRANS_VRR_FLIPLINE_B		0x61438
2077 #define _TRANS_VRR_FLIPLINE_C		0x62438
2078 #define _TRANS_VRR_FLIPLINE_D		0x63438
2081 #define   VRR_FLIPLINE_MASK		REG_GENMASK(19, 0)
2083 #define _TRANS_VRR_STATUS2_A		0x6043C
2084 #define _TRANS_VRR_STATUS2_B		0x6143C
2085 #define _TRANS_VRR_STATUS2_C		0x6243C
2086 #define _TRANS_VRR_STATUS2_D		0x6343C
2088 #define   VRR_STATUS2_VERT_LN_CNT_MASK	REG_GENMASK(19, 0)
2090 #define _TRANS_PUSH_A			0x60A70
2091 #define _TRANS_PUSH_B			0x61A70
2092 #define _TRANS_PUSH_C			0x62A70
2093 #define _TRANS_PUSH_D			0x63A70
2099 #define ADPA			_MMIO(0x61100)
2100 #define PCH_ADPA                _MMIO(0xe1100)
2101 #define VLV_ADPA		_MMIO(VLV_DISPLAY_BASE + 0x61100)
2104 #define   ADPA_DAC_DISABLE	0
2111 #define   ADPA_CRT_HOTPLUG_MASK  0x03ff0000 /* bit 25-16 */
2112 #define   ADPA_CRT_HOTPLUG_MONITOR_NONE  (0 << 24)
2117 #define   ADPA_CRT_HOTPLUG_PERIOD_64     (0 << 22)
2119 #define   ADPA_CRT_HOTPLUG_WARMUP_5MS    (0 << 21)
2121 #define   ADPA_CRT_HOTPLUG_SAMPLE_2S     (0 << 20)
2123 #define   ADPA_CRT_HOTPLUG_VOLTAGE_40    (0 << 18)
2127 #define   ADPA_CRT_HOTPLUG_VOLREF_325MV  (0 << 17)
2131 #define   ADPA_SETS_HVPOLARITY	0
2133 #define   ADPA_VSYNC_CNTL_ENABLE 0
2135 #define   ADPA_HSYNC_CNTL_ENABLE 0
2137 #define   ADPA_VSYNC_ACTIVE_LOW	0
2139 #define   ADPA_HSYNC_ACTIVE_LOW	0
2141 #define   ADPA_DPMS_ON		(0 << 10)
2148 #define PORT_HOTPLUG_EN		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110)
2163 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
2166 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
2168 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
2173 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
2175 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
2178 #define PORT_HOTPLUG_STAT	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114)
2198 #define   CRT_HOTPLUG_MONITOR_NONE		(0 << 8)
2233 #define _GEN3_SDVOB	0x61140
2234 #define _GEN3_SDVOC	0x61160
2239 #define VLV_HDMIB	_MMIO(VLV_DISPLAY_BASE + 0x61140)
2240 #define VLV_HDMIC	_MMIO(VLV_DISPLAY_BASE + 0x61160)
2241 #define CHV_HDMID	_MMIO(VLV_DISPLAY_BASE + 0x6116C)
2242 #define PCH_SDVOB	_MMIO(0xe1140)
2244 #define PCH_HDMIC	_MMIO(0xe1150)
2245 #define PCH_HDMID	_MMIO(0xe1160)
2247 #define PORT_DFT_I9XX				_MMIO(0x61150)
2249 #define PORT_DFT2_G4X		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154)
2251 #define   PIPE_SCRAMBLE_RESET_MASK		((1 << 14) | (0x3 << 0))
2254 #define   PIPE_A_SCRAMBLE_RESET			REG_BIT(0)
2283 #define   SDVO_COLOR_FORMAT_8bpc		(0 << 26)
2285 #define   SDVO_ENCODING_SDVO			(0 << 10)
2288 #define   HDMI_MODE_SELECT_DVI			(0 << 9) /* HDMI only */
2310 #define VIDEO_DIP_DATA		_MMIO(0x61178)
2318 #define VIDEO_DIP_CTL		_MMIO(0x61170)
2328 #define   VIDEO_DIP_SELECT_AVI		(0 << 19)
2333 #define   VIDEO_DIP_FREQ_ONCE		(0 << 16)
2340 #define   VSC_SELECT_MASK		(0x3 << 25)
2342 #define   VSC_DIP_HW_HEA_DATA		(0 << 25)
2352 #define   VIDEO_DIP_ENABLE_SPD_HSW	(1 << 0)
2355 #define PFIT_CONTROL	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230)
2360 #define   PFIT_SCALING_AUTO		REG_FIELD_PREP(PFIT_SCALING_MASK, 0)
2365 #define   PFIT_FILTER_FUZZY		REG_FIELD_PREP(PFIT_FILTER_MASK, 0)
2376 #define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234)
2382 #define   PFIT_HORIZ_SCALE_MASK_965	REG_GENMASK(12, 0) /* 965+ */
2384 #define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238)
2386 #define PCH_GTC_CTL		_MMIO(0xe7000)
2390 #define DP_A			_MMIO(0x64000) /* eDP */
2391 #define DP_B			_MMIO(0x64100)
2392 #define DP_C			_MMIO(0x64200)
2393 #define DP_D			_MMIO(0x64300)
2395 #define VLV_DP_B		_MMIO(VLV_DISPLAY_BASE + 0x64100)
2396 #define VLV_DP_C		_MMIO(VLV_DISPLAY_BASE + 0x64200)
2397 #define CHV_DP_D		_MMIO(VLV_DISPLAY_BASE + 0x64300)
2411 #define   DP_LINK_TRAIN_PAT_1		(0 << 28)
2419 #define   DP_LINK_TRAIN_PAT_1_CPT	(0 << 8)
2427 #define   DP_VOLTAGE_0_4		(0 << 25)
2437 #define   DP_PRE_EMPHASIS_0		(0 << 22)
2453 #define   DP_PLL_FREQ_270MHZ		(0 << 16)
2495 #define _PIPEA_DATA_M_G4X	0x70050
2496 #define _PIPEB_DATA_M_G4X	0x71050
2498 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2502 #define  DATA_LINK_M_N_MASK	REG_GENMASK(23, 0)
2503 #define  DATA_LINK_N_MAX	(0x800000)
2505 #define _PIPEA_DATA_N_G4X	0x70054
2506 #define _PIPEB_DATA_N_G4X	0x71054
2519 #define _PIPEA_LINK_M_G4X	0x70060
2520 #define _PIPEB_LINK_M_G4X	0x71060
2521 #define _PIPEA_LINK_N_G4X	0x70064
2522 #define _PIPEB_LINK_N_G4X	0x71064
2532 #define _PIPEADSL		0x70000
2534 #define   PIPEDSL_LINE_MASK	REG_GENMASK(19, 0)
2535 #define _TRANSACONF		0x70008
2541 …CONF_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
2546 #define   TRANSCONF_GAMMA_MODE_8BIT		REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
2552 #define   TRANSCONF_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
2563 #define   TRANSCONF_INTERLACE_PF_PD_ILK		REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
2576 #define   TRANSCONF_OUTPUT_COLORSPACE_RGB	REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* il…
2581 #define   TRANSCONF_BPC_8			REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
2587 #define   TRANSCONF_DITHER_TYPE_SP		REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
2591 #define _PIPEASTAT		0x70024
2636 #define   PIPE_HBLANK_INT_STATUS		(1UL << 0)
2637 #define   PIPE_OVERLAY_UPDATED_STATUS		(1UL << 0)
2639 #define PIPESTAT_INT_ENABLE_MASK		0x7fff0000
2640 #define PIPESTAT_INT_STATUS_MASK		0x0000ffff
2648 #define  _PIPEAGCMAX           0x70010
2649 #define  _PIPEBGCMAX           0x71010
2652 #define _PIPE_ARB_CTL_A			0x70028 /* icl+ */
2656 #define _PIPE_MISC_A			0x70030
2657 #define _PIPE_MISC_B			0x71030
2675 #define   PIPE_MISC_BPC_8			REG_FIELD_PREP(PIPE_MISC_BPC_MASK, 0)
2681 #define   PIPE_MISC_DITHER_TYPE_SP		REG_FIELD_PREP(PIPE_MISC_DITHER_TYPE_MASK, 0)
2687 #define _PIPE_MISC2_A					0x7002C
2688 #define _PIPE_MISC2_B					0x7102C
2692 #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */
2697 #define _SKL_BOTTOM_COLOR_A		0x70034
2698 #define _SKL_BOTTOM_COLOR_B		0x71034
2703 #define _ICL_PIPE_A_STATUS			0x70058
2710 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
2731 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
2746 #define   DPINVGTT_STATUS_MASK_CHV			REG_GENMASK(11, 0)
2747 #define   DPINVGTT_STATUS_MASK_VLV			REG_GENMASK(7, 0)
2759 #define   PLANEA_INVALID_GTT_STATUS			REG_BIT(0)
2761 #define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
2762 #define   DSPARB_CSTART_MASK	(0x7f << 7)
2764 #define   DSPARB_BSTART_MASK	(0x7f)
2765 #define   DSPARB_BSTART_SHIFT	0
2767 #define   DSPARB_AEND_SHIFT	0
2768 #define   DSPARB_SPRITEA_SHIFT_VLV	0
2769 #define   DSPARB_SPRITEA_MASK_VLV	(0xff << 0)
2771 #define   DSPARB_SPRITEB_MASK_VLV	(0xff << 8)
2773 #define   DSPARB_SPRITEC_MASK_VLV	(0xff << 16)
2775 #define   DSPARB_SPRITED_MASK_VLV	(0xff << 24)
2776 #define DSPARB2				_MMIO(VLV_DISPLAY_BASE + 0x70060) /* vlv/chv */
2777 #define   DSPARB_SPRITEA_HI_SHIFT_VLV	0
2778 #define   DSPARB_SPRITEA_HI_MASK_VLV	(0x1 << 0)
2780 #define   DSPARB_SPRITEB_HI_MASK_VLV	(0x1 << 4)
2782 #define   DSPARB_SPRITEC_HI_MASK_VLV	(0x1 << 8)
2784 #define   DSPARB_SPRITED_HI_MASK_VLV	(0x1 << 12)
2786 #define   DSPARB_SPRITEE_HI_MASK_VLV	(0x1 << 16)
2788 #define   DSPARB_SPRITEF_HI_MASK_VLV	(0x1 << 20)
2789 #define DSPARB3				_MMIO(VLV_DISPLAY_BASE + 0x7006c) /* chv */
2790 #define   DSPARB_SPRITEE_SHIFT_VLV	0
2791 #define   DSPARB_SPRITEE_MASK_VLV	(0xff << 0)
2793 #define   DSPARB_SPRITEF_MASK_VLV	(0xff << 8)
2796 #define DSPFW1		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034)
2798 #define   DSPFW_SR_MASK			(0x1ff << 23)
2800 #define   DSPFW_CURSORB_MASK		(0x3f << 16)
2802 #define   DSPFW_PLANEB_MASK		(0x7f << 8)
2803 #define   DSPFW_PLANEB_MASK_VLV		(0xff << 8) /* vlv/chv */
2804 #define   DSPFW_PLANEA_SHIFT		0
2805 #define   DSPFW_PLANEA_MASK		(0x7f << 0)
2806 #define   DSPFW_PLANEA_MASK_VLV		(0xff << 0) /* vlv/chv */
2807 #define DSPFW2		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038)
2810 #define   DSPFW_FBC_SR_MASK		(0x7 << 28) /* g4x */
2812 #define   DSPFW_FBC_HPLL_SR_MASK	(0xf << 24) /* g4x */
2814 #define   DSPFW_SPRITEB_MASK		(0x7f << 16) /* g4x */
2815 #define   DSPFW_SPRITEB_MASK_VLV	(0xff << 16) /* vlv/chv */
2817 #define   DSPFW_CURSORA_MASK		(0x3f << 8)
2818 #define   DSPFW_PLANEC_OLD_SHIFT	0
2819 #define   DSPFW_PLANEC_OLD_MASK		(0x7f << 0) /* pre-gen4 sprite C */
2820 #define   DSPFW_SPRITEA_SHIFT		0
2821 #define   DSPFW_SPRITEA_MASK		(0x7f << 0) /* g4x */
2822 #define   DSPFW_SPRITEA_MASK_VLV	(0xff << 0) /* vlv/chv */
2823 #define DSPFW3		_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c)
2827 #define   DSPFW_CURSOR_SR_MASK		(0x3f << 24)
2829 #define   DSPFW_HPLL_CURSOR_MASK	(0x3f << 16)
2830 #define   DSPFW_HPLL_SR_SHIFT		0
2831 #define   DSPFW_HPLL_SR_MASK		(0x1ff << 0)
2834 #define DSPFW4		_MMIO(VLV_DISPLAY_BASE + 0x70070)
2836 #define   DSPFW_SPRITEB_WM1_MASK	(0xff << 16)
2838 #define   DSPFW_CURSORA_WM1_MASK	(0x3f << 8)
2839 #define   DSPFW_SPRITEA_WM1_SHIFT	0
2840 #define   DSPFW_SPRITEA_WM1_MASK	(0xff << 0)
2841 #define DSPFW5		_MMIO(VLV_DISPLAY_BASE + 0x70074)
2843 #define   DSPFW_PLANEB_WM1_MASK		(0xff << 24)
2845 #define   DSPFW_PLANEA_WM1_MASK		(0xff << 16)
2847 #define   DSPFW_CURSORB_WM1_MASK	(0x3f << 8)
2848 #define   DSPFW_CURSOR_SR_WM1_SHIFT	0
2849 #define   DSPFW_CURSOR_SR_WM1_MASK	(0x3f << 0)
2850 #define DSPFW6		_MMIO(VLV_DISPLAY_BASE + 0x70078)
2851 #define   DSPFW_SR_WM1_SHIFT		0
2852 #define   DSPFW_SR_WM1_MASK		(0x1ff << 0)
2853 #define DSPFW7		_MMIO(VLV_DISPLAY_BASE + 0x7007c)
2854 #define DSPFW7_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b4) /* wtf #1? */
2856 #define   DSPFW_SPRITED_WM1_MASK	(0xff << 24)
2858 #define   DSPFW_SPRITED_MASK_VLV	(0xff << 16)
2860 #define   DSPFW_SPRITEC_WM1_MASK	(0xff << 8)
2861 #define   DSPFW_SPRITEC_SHIFT		0
2862 #define   DSPFW_SPRITEC_MASK_VLV	(0xff << 0)
2863 #define DSPFW8_CHV	_MMIO(VLV_DISPLAY_BASE + 0x700b8)
2865 #define   DSPFW_SPRITEF_WM1_MASK	(0xff << 24)
2867 #define   DSPFW_SPRITEF_MASK_VLV	(0xff << 16)
2869 #define   DSPFW_SPRITEE_WM1_MASK	(0xff << 8)
2870 #define   DSPFW_SPRITEE_SHIFT		0
2871 #define   DSPFW_SPRITEE_MASK_VLV	(0xff << 0)
2872 #define DSPFW9_CHV	_MMIO(VLV_DISPLAY_BASE + 0x7007c) /* wtf #2? */
2874 #define   DSPFW_PLANEC_WM1_MASK		(0xff << 24)
2876 #define   DSPFW_PLANEC_MASK_VLV		(0xff << 16)
2878 #define   DSPFW_CURSORC_WM1_MASK	(0x3f << 16)
2879 #define   DSPFW_CURSORC_SHIFT		0
2880 #define   DSPFW_CURSORC_MASK		(0x3f << 0)
2883 #define DSPHOWM		_MMIO(VLV_DISPLAY_BASE + 0x70064)
2902 #define   DSPFW_PLANEA_HI_SHIFT		0
2903 #define   DSPFW_PLANEA_HI_MASK		(1 << 0)
2904 #define DSPHOWM1	_MMIO(VLV_DISPLAY_BASE + 0x70068)
2923 #define   DSPFW_PLANEA_WM1_HI_SHIFT	0
2924 #define   DSPFW_PLANEA_WM1_HI_MASK	(1 << 0)
2927 #define VLV_DDL(pipe)			_MMIO(VLV_DISPLAY_BASE + 0x70050 + 4 * (pipe))
2930 #define DDL_PLANE_SHIFT			0
2932 #define DDL_PRECISION_LOW		(0 << 7)
2933 #define DRAIN_LATENCY_MASK		0x7f
2935 #define CBR1_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70400)
2939 #define CBR4_VLV			_MMIO(VLV_DISPLAY_BASE + 0x70450)
2955 #define VALLEYVIEW_MAX_WM	0xff
2956 #define G4X_MAX_WM		0x3f
2957 #define I915_MAX_WM		0x3f
2961 #define PINEVIEW_MAX_WM		0x1ff
2962 #define PINEVIEW_DFT_WM		0x3f
2963 #define PINEVIEW_DFT_HPLLOFF_WM	0
2966 #define PINEVIEW_CURSOR_MAX_WM	0x3f
2967 #define PINEVIEW_CURSOR_DFT_WM	0
2976 #define _WM0_PIPEA_ILK		0x45100
2977 #define _WM0_PIPEB_ILK		0x45104
2978 #define _WM0_PIPEC_IVB		0x45200
2983 #define  WM0_PIPE_CURSOR_MASK	REG_GENMASK(7, 0)
2987 #define WM1_LP_ILK		_MMIO(0x45108)
2988 #define WM2_LP_ILK		_MMIO(0x4510c)
2989 #define WM3_LP_ILK		_MMIO(0x45110)
2995 #define  WM_LP_CURSOR_MASK	REG_GENMASK(7, 0)
3001 #define WM1S_LP_ILK		_MMIO(0x45120)
3002 #define WM2S_LP_IVB		_MMIO(0x45124)
3003 #define WM3S_LP_IVB		_MMIO(0x45128)
3005 #define  WM_LP_SPRITE_MASK	REG_GENMASK(10, 0)
3023 #define _PIPEAFRAMEHIGH          0x70040
3024 #define   PIPE_FRAME_HIGH_MASK    0x0000ffff
3025 #define   PIPE_FRAME_HIGH_SHIFT   0
3026 #define _PIPEAFRAMEPIXEL         0x70044
3027 #define   PIPE_FRAME_LOW_MASK     0xff000000
3029 #define   PIPE_PIXEL_MASK         0x00ffffff
3030 #define   PIPE_PIXEL_SHIFT        0
3032 #define _PIPEA_FRMCOUNT_G4X	0x70040
3033 #define _PIPEA_FLIPCOUNT_G4X	0x70044
3038 #define _CURACNTR		0x70080
3045 #define   CURSOR_FORMAT_2C	REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0)
3059 #define   MCURSOR_MODE_MASK		0x27
3060 #define   MCURSOR_MODE_DISABLE		0x00
3061 #define   MCURSOR_MODE_128_32B_AX	0x02
3062 #define   MCURSOR_MODE_256_32B_AX	0x03
3063 #define   MCURSOR_MODE_64_32B_AX	0x07
3064 #define   MCURSOR_MODE_128_ARGB_AX	(0x20 | MCURSOR_MODE_128_32B_AX)
3065 #define   MCURSOR_MODE_256_ARGB_AX	(0x20 | MCURSOR_MODE_256_32B_AX)
3066 #define   MCURSOR_MODE_64_ARGB_AX	(0x20 | MCURSOR_MODE_64_32B_AX)
3067 #define _CURABASE		0x70084
3068 #define _CURAPOS		0x70088
3073 #define   CURSOR_POS_X_MASK		REG_GENMASK(14, 0)
3075 #define _CURASIZE		0x700a0 /* 845/865 */
3078 #define   CURSOR_WIDTH_MASK		REG_GENMASK(9, 0)
3080 #define _CUR_FBC_CTL_A		0x700a0 /* ivb+ */
3082 #define   CUR_FBC_HEIGHT_MASK		REG_GENMASK(7, 0)
3084 #define _CUR_CHICKEN_A		0x700a4 /* mtl+ */
3085 #define _CURASURFLIVE		0x700ac /* g4x+ */
3086 #define _CURBCNTR		0x700c0
3087 #define _CURBBASE		0x700c4
3088 #define _CURBPOS		0x700c8
3090 #define _CURBCNTR_IVB		0x71080
3091 #define _CURBBASE_IVB		0x71084
3092 #define _CURBPOS_IVB		0x71088
3103 #define _DSPAADDR_VLV				0x7017C /* vlv/chv */
3104 #define _DSPACNTR				0x70180
3134 #define _DSPAADDR				0x70184
3135 #define _DSPASTRIDE				0x70188
3136 #define _DSPAPOS				0x7018C /* reserved */
3139 #define   DISP_POS_X_MASK		REG_GENMASK(15, 0)
3141 #define _DSPASIZE				0x70190
3144 #define   DISP_WIDTH_MASK		REG_GENMASK(15, 0)
3146 #define _DSPASURF				0x7019C /* 965+ only */
3148 #define _DSPATILEOFF				0x701A4 /* 965+ only */
3151 #define   DISP_OFFSET_X_MASK		REG_GENMASK(15, 0)
3153 #define _DSPAOFFSET				0x701A4 /* HSW */
3154 #define _DSPASURFLIVE				0x701AC
3155 #define _DSPAGAMC				0x701E0
3171 #define _CHV_BLEND_A		0x60a00
3173 #define   CHV_BLEND_LEGACY	REG_FIELD_PREP(CHV_BLEND_MASK, 0)
3176 #define _CHV_CANVAS_A		0x60a04
3179 #define   CHV_CANVAS_BLUE_MASK	REG_GENMASK(9, 0)
3180 #define _PRIMPOS_A		0x60a08
3183 #define   PRIM_POS_X_MASK	REG_GENMASK(15, 0)
3185 #define _PRIMSIZE_A		0x60a0c
3188 #define   PRIM_WIDTH_MASK	REG_GENMASK(15, 0)
3190 #define _PRIMCNSTALPHA_A	0x60a10
3192 #define   PRIM_CONST_ALPHA_MASK		REG_GENMASK(7, 0)
3202 #define DISP_BASEADDR_MASK	(0xfffff000)
3213  * [00:0f] all
3217 #define SWF0(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4)
3218 #define SWF1(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4)
3219 #define SWF3(i)	_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
3220 #define SWF_ILK(i)	_MMIO(0x4F000 + (i) * 4)
3223 #define _PIPEBDSL		(DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
3224 #define _TRANSBCONF		(DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
3225 #define _PIPEBSTAT		(DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
3226 #define _PIPEBFRAMEHIGH		0x71040
3227 #define _PIPEBFRAMEPIXEL	0x71044
3228 #define _PIPEB_FRMCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71040)
3229 #define _PIPEB_FLIPCOUNT_G4X	(DISPLAY_MMIO_BASE(dev_priv) + 0x71044)
3233 #define _DSPBCNTR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71180)
3235 #define   DISP_SPRITE_ABOVE_OVERLAY	REG_BIT(0)
3236 #define _DSPBADDR		(DISPLAY_MMIO_BASE(dev_priv) + 0x71184)
3237 #define _DSPBSTRIDE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71188)
3238 #define _DSPBPOS		(DISPLAY_MMIO_BASE(dev_priv) + 0x7118C)
3239 #define _DSPBSIZE		(DISPLAY_MMIO_BASE(dev_priv) + 0x71190)
3240 #define _DSPBSURF		(DISPLAY_MMIO_BASE(dev_priv) + 0x7119C)
3241 #define _DSPBTILEOFF		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
3242 #define _DSPBOFFSET		(DISPLAY_MMIO_BASE(dev_priv) + 0x711A4)
3243 #define _DSPBSURFLIVE		(DISPLAY_MMIO_BASE(dev_priv) + 0x711AC)
3245 /* ICL DSI 0 and 1 */
3246 #define _PIPEDSI0CONF		0x7b008
3247 #define _PIPEDSI1CONF		0x7b808
3250 #define _DVSACNTR		0x72180
3255 #define   DVS_FORMAT_YUV422		REG_FIELD_PREP(DVS_FORMAT_MASK, 0)
3264 #define   DVS_YUV_ORDER_YUYV		REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0)
3272 #define _DVSALINOFF		0x72184
3273 #define _DVSASTRIDE		0x72188
3274 #define _DVSAPOS		0x7218c
3277 #define   DVS_POS_X_MASK		REG_GENMASK(15, 0)
3279 #define _DVSASIZE		0x72190
3282 #define   DVS_WIDTH_MASK		REG_GENMASK(15, 0)
3284 #define _DVSAKEYVAL		0x72194
3285 #define _DVSAKEYMSK		0x72198
3286 #define _DVSASURF		0x7219c
3288 #define _DVSAKEYMAXVAL		0x721a0
3289 #define _DVSATILEOFF		0x721a4
3292 #define   DVS_OFFSET_X_MASK		REG_GENMASK(15, 0)
3294 #define _DVSASURFLIVE		0x721ac
3295 #define _DVSAGAMC_G4X		0x721e0 /* g4x */
3296 #define _DVSASCALE		0x72204
3299 #define   DVS_FILTER_MEDIUM		REG_FIELD_PREP(DVS_FILTER_MASK, 0)
3306 #define   DVS_SRC_HEIGHT_MASK		REG_GENMASK(10, 0)
3308 #define _DVSAGAMC_ILK		0x72300 /* ilk/snb */
3309 #define _DVSAGAMCMAX_ILK	0x72340 /* ilk/snb */
3311 #define _DVSBCNTR		0x73180
3312 #define _DVSBLINOFF		0x73184
3313 #define _DVSBSTRIDE		0x73188
3314 #define _DVSBPOS		0x7318c
3315 #define _DVSBSIZE		0x73190
3316 #define _DVSBKEYVAL		0x73194
3317 #define _DVSBKEYMSK		0x73198
3318 #define _DVSBSURF		0x7319c
3319 #define _DVSBKEYMAXVAL		0x731a0
3320 #define _DVSBTILEOFF		0x731a4
3321 #define _DVSBSURFLIVE		0x731ac
3322 #define _DVSBGAMC_G4X		0x731e0 /* g4x */
3323 #define _DVSBSCALE		0x73204
3324 #define _DVSBGAMC_ILK		0x73300 /* ilk/snb */
3325 #define _DVSBGAMCMAX_ILK	0x73340 /* ilk/snb */
3343 #define _SPRA_CTL		0x70280
3348 #define   SPRITE_FORMAT_YUV422			REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0)
3358 #define   SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709	REG_BIT(18) /* 0 is BT601 */
3360 #define   SPRITE_YUV_ORDER_YUYV			REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0)
3369 #define _SPRA_LINOFF		0x70284
3370 #define _SPRA_STRIDE		0x70288
3371 #define _SPRA_POS		0x7028c
3374 #define   SPRITE_POS_X_MASK	REG_GENMASK(15, 0)
3376 #define _SPRA_SIZE		0x70290
3379 #define   SPRITE_WIDTH_MASK	REG_GENMASK(15, 0)
3381 #define _SPRA_KEYVAL		0x70294
3382 #define _SPRA_KEYMSK		0x70298
3383 #define _SPRA_SURF		0x7029c
3385 #define _SPRA_KEYMAX		0x702a0
3386 #define _SPRA_TILEOFF		0x702a4
3389 #define   SPRITE_OFFSET_X_MASK	REG_GENMASK(15, 0)
3391 #define _SPRA_OFFSET		0x702a4
3392 #define _SPRA_SURFLIVE		0x702ac
3393 #define _SPRA_SCALE		0x70304
3396 #define   SPRITE_FILTER_MEDIUM			REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
3403 #define   SPRITE_SRC_HEIGHT_MASK		REG_GENMASK(10, 0)
3405 #define _SPRA_GAMC		0x70400
3406 #define _SPRA_GAMC16		0x70440
3407 #define _SPRA_GAMC17		0x7044c
3409 #define _SPRB_CTL		0x71280
3410 #define _SPRB_LINOFF		0x71284
3411 #define _SPRB_STRIDE		0x71288
3412 #define _SPRB_POS		0x7128c
3413 #define _SPRB_SIZE		0x71290
3414 #define _SPRB_KEYVAL		0x71294
3415 #define _SPRB_KEYMSK		0x71298
3416 #define _SPRB_SURF		0x7129c
3417 #define _SPRB_KEYMAX		0x712a0
3418 #define _SPRB_TILEOFF		0x712a4
3419 #define _SPRB_OFFSET		0x712a4
3420 #define _SPRB_SURFLIVE		0x712ac
3421 #define _SPRB_SCALE		0x71304
3422 #define _SPRB_GAMC		0x71400
3423 #define _SPRB_GAMC16		0x71440
3424 #define _SPRB_GAMC17		0x7144c
3443 #define _SPACNTR		(VLV_DISPLAY_BASE + 0x72180)
3447 #define   SP_FORMAT_YUV422		REG_FIELD_PREP(SP_FORMAT_MASK, 0)
3462 #define   SP_YUV_ORDER_YUYV		REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0)
3469 #define _SPALINOFF		(VLV_DISPLAY_BASE + 0x72184)
3470 #define _SPASTRIDE		(VLV_DISPLAY_BASE + 0x72188)
3471 #define _SPAPOS			(VLV_DISPLAY_BASE + 0x7218c)
3474 #define   SP_POS_X_MASK			REG_GENMASK(15, 0)
3476 #define _SPASIZE		(VLV_DISPLAY_BASE + 0x72190)
3479 #define   SP_WIDTH_MASK			REG_GENMASK(15, 0)
3481 #define _SPAKEYMINVAL		(VLV_DISPLAY_BASE + 0x72194)
3482 #define _SPAKEYMSK		(VLV_DISPLAY_BASE + 0x72198)
3483 #define _SPASURF		(VLV_DISPLAY_BASE + 0x7219c)
3485 #define _SPAKEYMAXVAL		(VLV_DISPLAY_BASE + 0x721a0)
3486 #define _SPATILEOFF		(VLV_DISPLAY_BASE + 0x721a4)
3489 #define   SP_OFFSET_X_MASK		REG_GENMASK(15, 0)
3491 #define _SPACONSTALPHA		(VLV_DISPLAY_BASE + 0x721a8)
3493 #define   SP_CONST_ALPHA_MASK		REG_GENMASK(7, 0)
3495 #define _SPASURFLIVE		(VLV_DISPLAY_BASE + 0x721ac)
3496 #define _SPACLRC0		(VLV_DISPLAY_BASE + 0x721d0)
3499 #define   SP_BRIGHTNESS_MASK		REG_GENMASK(7, 0)
3501 #define _SPACLRC1		(VLV_DISPLAY_BASE + 0x721d4)
3504 #define   SP_SH_COS_MASK		REG_GENMASK(9, 0)
3506 #define _SPAGAMC		(VLV_DISPLAY_BASE + 0x721e0)
3508 #define _SPBCNTR		(VLV_DISPLAY_BASE + 0x72280)
3509 #define _SPBLINOFF		(VLV_DISPLAY_BASE + 0x72284)
3510 #define _SPBSTRIDE		(VLV_DISPLAY_BASE + 0x72288)
3511 #define _SPBPOS			(VLV_DISPLAY_BASE + 0x7228c)
3512 #define _SPBSIZE		(VLV_DISPLAY_BASE + 0x72290)
3513 #define _SPBKEYMINVAL		(VLV_DISPLAY_BASE + 0x72294)
3514 #define _SPBKEYMSK		(VLV_DISPLAY_BASE + 0x72298)
3515 #define _SPBSURF		(VLV_DISPLAY_BASE + 0x7229c)
3516 #define _SPBKEYMAXVAL		(VLV_DISPLAY_BASE + 0x722a0)
3517 #define _SPBTILEOFF		(VLV_DISPLAY_BASE + 0x722a4)
3518 #define _SPBCONSTALPHA		(VLV_DISPLAY_BASE + 0x722a8)
3519 #define _SPBSURFLIVE		(VLV_DISPLAY_BASE + 0x722ac)
3520 #define _SPBCLRC0		(VLV_DISPLAY_BASE + 0x722d0)
3521 #define _SPBCLRC1		(VLV_DISPLAY_BASE + 0x722d4)
3522 #define _SPBGAMC		(VLV_DISPLAY_BASE + 0x722e0)
3553 	_MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
3555 #define SPCSCYGOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d900)
3556 #define SPCSCCBOFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d904)
3557 #define SPCSCCROFF(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d908)
3559 #define  SPCSC_OOFF(x)		REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */
3560 #define  SPCSC_IOFF_MASK	REG_GENMASK(10, 0)
3561 #define  SPCSC_IOFF(x)		REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */
3563 #define SPCSCC01(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d90c)
3564 #define SPCSCC23(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d910)
3565 #define SPCSCC45(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d914)
3566 #define SPCSCC67(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d918)
3567 #define SPCSCC8(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d91c)
3569 #define  SPCSC_C1(x)		REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */
3570 #define  SPCSC_C0_MASK		REG_GENMASK(14, 0)
3571 #define  SPCSC_C0(x)		REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */
3573 #define SPCSCYGICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d920)
3574 #define SPCSCCBICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d924)
3575 #define SPCSCCRICLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d928)
3577 #define  SPCSC_IMAX(x)		REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */
3578 #define  SPCSC_IMIN_MASK	REG_GENMASK(10, 0)
3579 #define  SPCSC_IMIN(x)		REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */
3581 #define SPCSCYGOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d92c)
3582 #define SPCSCCBOCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d930)
3583 #define SPCSCCROCLAMP(plane_id)	_MMIO_CHV_SPCSC(plane_id, 0x6d934)
3586 #define  SPCSC_OMIN_MASK	REG_GENMASK(9, 0)
3591 #define _PLANE_CTL_1_A				0x70180
3592 #define _PLANE_CTL_2_A				0x70280
3593 #define _PLANE_CTL_3_A				0x70380
3602  * correctly map to the same formats in ICL, as long as bit 23 is set to 0
3606 #define   PLANE_CTL_FORMAT_YUV422		REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0)
3631 #define   PLANE_CTL_YUV422_ORDER_YUYV		REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0)
3640 #define   PLANE_CTL_TILED_LINEAR		REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0)
3649 #define   PLANE_CTL_ALPHA_DISABLE		REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0)
3652 #define   PLANE_CTL_ROTATE_MASK			REG_GENMASK(1, 0)
3653 #define   PLANE_CTL_ROTATE_0			REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0)
3657 #define _PLANE_STRIDE_1_A			0x70188
3658 #define _PLANE_STRIDE_2_A			0x70288
3659 #define _PLANE_STRIDE_3_A			0x70388
3660 #define   PLANE_STRIDE__MASK			REG_GENMASK(11, 0)
3662 #define _PLANE_POS_1_A				0x7018c
3663 #define _PLANE_POS_2_A				0x7028c
3664 #define _PLANE_POS_3_A				0x7038c
3667 #define   PLANE_POS_X_MASK			REG_GENMASK(15, 0)
3669 #define _PLANE_SIZE_1_A				0x70190
3670 #define _PLANE_SIZE_2_A				0x70290
3671 #define _PLANE_SIZE_3_A				0x70390
3674 #define   PLANE_WIDTH_MASK			REG_GENMASK(15, 0)
3676 #define _PLANE_SURF_1_A				0x7019c
3677 #define _PLANE_SURF_2_A				0x7029c
3678 #define _PLANE_SURF_3_A				0x7039c
3681 #define _PLANE_OFFSET_1_A			0x701a4
3682 #define _PLANE_OFFSET_2_A			0x702a4
3683 #define _PLANE_OFFSET_3_A			0x703a4
3686 #define   PLANE_OFFSET_X_MASK			REG_GENMASK(15, 0)
3688 #define _PLANE_KEYVAL_1_A			0x70194
3689 #define _PLANE_KEYVAL_2_A			0x70294
3690 #define _PLANE_KEYMSK_1_A			0x70198
3691 #define _PLANE_KEYMSK_2_A			0x70298
3693 #define _PLANE_KEYMAX_1_A			0x701a0
3694 #define _PLANE_KEYMAX_2_A			0x702a0
3697 #define _PLANE_SURFLIVE_1_A			0x701ac
3698 #define _PLANE_SURFLIVE_2_A			0x702ac
3699 #define _PLANE_CC_VAL_1_A			0x701b4
3700 #define _PLANE_CC_VAL_2_A			0x702b4
3701 #define _PLANE_AUX_DIST_1_A			0x701c0
3703 #define   PLANE_AUX_STRIDE_MASK			REG_GENMASK(11, 0)
3705 #define _PLANE_AUX_DIST_2_A			0x702c0
3706 #define _PLANE_AUX_OFFSET_1_A			0x701c4
3707 #define _PLANE_AUX_OFFSET_2_A			0x702c4
3708 #define _PLANE_CUS_CTL_1_A			0x701c8
3709 #define _PLANE_CUS_CTL_2_A			0x702c8
3712 #define   PLANE_CUS_Y_PLANE_4_RKL		REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
3714 #define   PLANE_CUS_Y_PLANE_6_ICL		REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0)
3718 #define   PLANE_CUS_HPHASE_0			REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0)
3723 #define   PLANE_CUS_VPHASE_0			REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0)
3726 #define _PLANE_COLOR_CTL_1_A			0x701CC /* GLK+ */
3727 #define _PLANE_COLOR_CTL_2_A			0x702CC /* GLK+ */
3728 #define _PLANE_COLOR_CTL_3_A			0x703CC /* GLK+ */
3735 #define   PLANE_COLOR_CSC_MODE_BYPASS			REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0)
3742 #define   PLANE_COLOR_ALPHA_DISABLE			REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0)
3745 #define _PLANE_CHICKEN_1_A			0x7026C /* tgl+ */
3746 #define _PLANE_CHICKEN_2_A			0x7036C /* tgl+ */
3748 #define _PLANE_BUF_CFG_1_A			0x7027c
3749 #define _PLANE_BUF_CFG_2_A			0x7037c
3753 #define   PLANE_BUF_START_MASK		REG_GENMASK(11, 0)
3755 #define _PLANE_NV12_BUF_CFG_1_A		0x70278
3756 #define _PLANE_NV12_BUF_CFG_2_A		0x70378
3758 #define _PLANE_CC_VAL_1_B		0x711b4
3759 #define _PLANE_CC_VAL_2_B		0x712b4
3766 #define _PLANE_INPUT_CSC_RY_GY_1_A	0x701E0
3767 #define _PLANE_INPUT_CSC_RY_GY_2_A	0x702E0
3769 #define _PLANE_INPUT_CSC_RY_GY_1_B	0x711E0
3770 #define _PLANE_INPUT_CSC_RY_GY_2_B	0x712E0
3783 #define _PLANE_INPUT_CSC_PREOFF_HI_1_A		0x701F8
3784 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A		0x702F8
3786 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B		0x711F8
3787 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B		0x712F8
3799 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A		0x70204
3800 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A		0x70304
3802 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B		0x71204
3803 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B		0x71304
3815 #define _PLANE_CTL_1_B				0x71180
3816 #define _PLANE_CTL_2_B				0x71280
3817 #define _PLANE_CTL_3_B				0x71380
3824 #define _PLANE_STRIDE_1_B			0x71188
3825 #define _PLANE_STRIDE_2_B			0x71288
3826 #define _PLANE_STRIDE_3_B			0x71388
3836 #define _PLANE_POS_1_B				0x7118c
3837 #define _PLANE_POS_2_B				0x7128c
3838 #define _PLANE_POS_3_B				0x7138c
3845 #define _PLANE_SIZE_1_B				0x71190
3846 #define _PLANE_SIZE_2_B				0x71290
3847 #define _PLANE_SIZE_3_B				0x71390
3854 #define _PLANE_SURF_1_B				0x7119c
3855 #define _PLANE_SURF_2_B				0x7129c
3856 #define _PLANE_SURF_3_B				0x7139c
3863 #define _PLANE_OFFSET_1_B			0x711a4
3864 #define _PLANE_OFFSET_2_B			0x712a4
3870 #define _PLANE_KEYVAL_1_B			0x71194
3871 #define _PLANE_KEYVAL_2_B			0x71294
3877 #define _PLANE_KEYMSK_1_B			0x71198
3878 #define _PLANE_KEYMSK_2_B			0x71298
3884 #define _PLANE_KEYMAX_1_B			0x711a0
3885 #define _PLANE_KEYMAX_2_B			0x712a0
3891 #define _PLANE_SURFLIVE_1_B			0x711ac
3892 #define _PLANE_SURFLIVE_2_B			0x712ac
3898 #define _PLANE_CHICKEN_1_B			0x7126c
3899 #define _PLANE_CHICKEN_2_B			0x7136c
3905 #define _PLANE_AUX_DIST_1_B		0x711c0
3906 #define _PLANE_AUX_DIST_2_B		0x712c0
3914 #define _PLANE_AUX_OFFSET_1_B		0x711c4
3915 #define _PLANE_AUX_OFFSET_2_B		0x712c4
3923 #define _PLANE_CUS_CTL_1_B		0x711c8
3924 #define _PLANE_CUS_CTL_2_B		0x712c8
3932 #define _PLANE_COLOR_CTL_1_B			0x711CC
3933 #define _PLANE_COLOR_CTL_2_B			0x712CC
3934 #define _PLANE_COLOR_CTL_3_B			0x713CC
3943 #define VGACNTRL		_MMIO(0x71400)
3948 #define VLV_VGACNTRL		_MMIO(VLV_DISPLAY_BASE + 0x71400)
3952 #define CPU_VGACNTRL	_MMIO(0x41000)
3954 #define DIGITAL_PORT_HOTPLUG_CNTRL	_MMIO(0x44030)
3956 #define  DIGITAL_PORTA_PULSE_DURATION_2ms	(0 << 2) /* pre-HSW */
3961 #define  DIGITAL_PORTA_HOTPLUG_STATUS_MASK	(3 << 0)
3962 #define  DIGITAL_PORTA_HOTPLUG_NO_DETECT	(0 << 0)
3963 #define  DIGITAL_PORTA_HOTPLUG_SHORT_DETECT	(1 << 0)
3964 #define  DIGITAL_PORTA_HOTPLUG_LONG_DETECT	(2 << 0)
3967 #define RR_HW_CTL       _MMIO(0x45300)
3968 #define  RR_HW_LOW_POWER_FRAMES_MASK    0xff
3969 #define  RR_HW_HIGH_POWER_FRAMES_MASK   0xff00
3971 #define PCH_3DCGDIS0		_MMIO(0x46020)
3975 #define PCH_3DCGDIS1		_MMIO(0x46024)
3978 #define _PIPEA_DATA_M1		0x60030
3979 #define _PIPEA_DATA_N1		0x60034
3980 #define _PIPEA_DATA_M2		0x60038
3981 #define _PIPEA_DATA_N2		0x6003c
3982 #define _PIPEA_LINK_M1		0x60040
3983 #define _PIPEA_LINK_N1		0x60044
3984 #define _PIPEA_LINK_M2		0x60048
3985 #define _PIPEA_LINK_N2		0x6004c
3987 /* PIPEB timing regs are same start from 0x61000 */
3989 #define _PIPEB_DATA_M1		0x61030
3990 #define _PIPEB_DATA_N1		0x61034
3991 #define _PIPEB_DATA_M2		0x61038
3992 #define _PIPEB_DATA_N2		0x6103c
3993 #define _PIPEB_LINK_M1		0x61040
3994 #define _PIPEB_LINK_N1		0x61044
3995 #define _PIPEB_LINK_M2		0x61048
3996 #define _PIPEB_LINK_N2		0x6104c
4008 /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
4009 #define _PFA_CTL_1		0x68080
4010 #define _PFB_CTL_1		0x68880
4015 #define   PF_FILTER_PROGRAMMED		REG_FIELD_PREP(PF_FILTER_MASK, 0)
4019 #define _PFA_WIN_SZ		0x68074
4020 #define _PFB_WIN_SZ		0x68874
4023 #define   PF_WIN_YSIZE_MASK	REG_GENMASK(15, 0)
4025 #define _PFA_WIN_POS		0x68070
4026 #define _PFB_WIN_POS		0x68870
4029 #define   PF_WIN_YPOS_MASK	REG_GENMASK(15, 0)
4031 #define _PFA_VSCALE		0x68084
4032 #define _PFB_VSCALE		0x68884
4033 #define _PFA_HSCALE		0x68090
4034 #define _PFB_HSCALE		0x68890
4045 #define _PS_1A_CTRL      0x68180
4046 #define _PS_2A_CTRL      0x68280
4047 #define _PS_1B_CTRL      0x68980
4048 #define _PS_2B_CTRL      0x68A80
4049 #define _PS_1C_CTRL      0x69180
4052 #define   PS_SCALER_TYPE_NON_LINEAR		REG_FIELD_PREP(PS_SCALER_TYPE_MASK, 0)
4055 #define   SKL_PS_SCALER_MODE_DYN		REG_FIELD_PREP(SKL_PS_SCALER_MODE_MASK, 0)
4059 #define   PS_SCALER_MODE_NORMAL			REG_FIELD_PREP(PS_SCALER_MODE_MASK, 0)
4063 #define   PS_BINDING_PIPE			REG_FIELD_PREP(PS_BINDING_MASK, 0)
4066 #define   PS_FILTER_MEDIUM			REG_FIELD_PREP(PS_FILTER_MASK, 0)
4071 #define   PS_ADAPTIVE_FILTER_MEDIUM		REG_FIELD_PREP(PS_ADAPTIVE_FILTER_MASK, 0)
4074 #define   PS_PIPE_SCALER_LOC_AFTER_OUTPUT_CSC	REG_FIELD_PREP(PS_SCALER_LOCATION_MASK, 0) /* non-lin…
4083 #define   PS_VADAPT_MODE_LEAST_ADAPT		REG_FIELD_PREP(PS_VADAPT_MODE_MASK, 0)
4097 #define _PS_PWR_GATE_1A     0x68160
4098 #define _PS_PWR_GATE_2A     0x68260
4099 #define _PS_PWR_GATE_1B     0x68960
4100 #define _PS_PWR_GATE_2B     0x68A60
4101 #define _PS_PWR_GATE_1C     0x69160
4104 #define   PS_PWR_GATE_SETTLING_TIME_32		REG_FIELD_PREP(PS_PWR_GATE_SETTLING_TIME_MASK, 0)
4108 #define   PS_PWR_GATE_SLPEN_MASK		REG_GENMASK(1, 0)
4109 #define   PS_PWR_GATE_SLPEN_8			REG_FIELD_PREP(PS_PWR_GATE_SLPEN_MASK, 0)
4114 #define _PS_WIN_POS_1A      0x68170
4115 #define _PS_WIN_POS_2A      0x68270
4116 #define _PS_WIN_POS_1B      0x68970
4117 #define _PS_WIN_POS_2B      0x68A70
4118 #define _PS_WIN_POS_1C      0x69170
4121 #define   PS_WIN_YPOS_MASK			REG_GENMASK(15, 0)
4124 #define _PS_WIN_SZ_1A       0x68174
4125 #define _PS_WIN_SZ_2A       0x68274
4126 #define _PS_WIN_SZ_1B       0x68974
4127 #define _PS_WIN_SZ_2B       0x68A74
4128 #define _PS_WIN_SZ_1C       0x69174
4131 #define   PS_WIN_YSIZE_MASK			REG_GENMASK(15, 0)
4134 #define _PS_VSCALE_1A       0x68184
4135 #define _PS_VSCALE_2A       0x68284
4136 #define _PS_VSCALE_1B       0x68984
4137 #define _PS_VSCALE_2B       0x68A84
4138 #define _PS_VSCALE_1C       0x69184
4140 #define _PS_HSCALE_1A       0x68190
4141 #define _PS_HSCALE_2A       0x68290
4142 #define _PS_HSCALE_1B       0x68990
4143 #define _PS_HSCALE_2B       0x68A90
4144 #define _PS_HSCALE_1C       0x69190
4146 #define _PS_VPHASE_1A       0x68188
4147 #define _PS_VPHASE_2A       0x68288
4148 #define _PS_VPHASE_1B       0x68988
4149 #define _PS_VPHASE_2B       0x68A88
4150 #define _PS_VPHASE_1C       0x69188
4153 #define   PS_UV_RGB_PHASE_MASK			REG_GENMASK(15, 0)
4155 #define   PS_PHASE_MASK				(0x7fff << 1) /* u2.13 */
4156 #define   PS_PHASE_TRIP				(1 << 0)
4158 #define _PS_HPHASE_1A       0x68194
4159 #define _PS_HPHASE_2A       0x68294
4160 #define _PS_HPHASE_1B       0x68994
4161 #define _PS_HPHASE_2B       0x68A94
4162 #define _PS_HPHASE_1C       0x69194
4164 #define _PS_ECC_STAT_1A     0x681D0
4165 #define _PS_ECC_STAT_2A     0x682D0
4166 #define _PS_ECC_STAT_1B     0x689D0
4167 #define _PS_ECC_STAT_2B     0x68AD0
4168 #define _PS_ECC_STAT_1C     0x691D0
4170 #define _PS_COEF_SET0_INDEX_1A	   0x68198
4171 #define _PS_COEF_SET0_INDEX_2A	   0x68298
4172 #define _PS_COEF_SET0_INDEX_1B	   0x68998
4173 #define _PS_COEF_SET0_INDEX_2B	   0x68A98
4176 #define _PS_COEF_SET0_DATA_1A	   0x6819C
4177 #define _PS_COEF_SET0_DATA_2A	   0x6829C
4178 #define _PS_COEF_SET0_DATA_1B	   0x6899C
4179 #define _PS_COEF_SET0_DATA_2B	   0x68A9C
4217 #define _LGC_PALETTE_A           0x4a000
4218 #define _LGC_PALETTE_B           0x4a800
4223 #define _PREC_PALETTE_A           0x4b000
4224 #define _PREC_PALETTE_B           0x4c000
4228 #define   PREC_PALETTE_10_BLUE_MASK		REG_GENMASK(9, 0)
4236 #define   PREC_PALETTE_12P4_BLUE_UDW_MASK	REG_GENMASK(9, 0)
4239 #define  _PREC_PIPEAGCMAX              0x4d000
4240 #define  _PREC_PIPEBGCMAX              0x4d010
4243 #define _GAMMA_MODE_A		0x4a480
4244 #define _GAMMA_MODE_B		0x4ac80
4249 #define  GAMMA_MODE_MODE_MASK			REG_GENMASK(1, 0)
4250 #define  GAMMA_MODE_MODE_8BIT			REG_FIELD_PREP(GAMMA_MODE_MODE_MASK, 0)
4257 #define RM_TIMEOUT		_MMIO(0x42060)
4258 #define  MMIO_TIMEOUT_US(us)	((us) << 0)
4290 #define DE_PIPEA_FIFO_UNDERRUN  (1 << 0)
4309 #define DE_PIPEA_VBLANK_IVB		(1 << 0)
4312 #define VLV_MASTER_IER			_MMIO(0x4400c) /* Gunit master IER */
4315 #define DEISR   _MMIO(0x44000)
4316 #define DEIMR   _MMIO(0x44004)
4317 #define DEIIR   _MMIO(0x44008)
4318 #define DEIER   _MMIO(0x4400c)
4320 #define GTISR   _MMIO(0x44010)
4321 #define GTIMR   _MMIO(0x44014)
4322 #define GTIIR   _MMIO(0x44018)
4323 #define GTIER   _MMIO(0x4401c)
4325 #define GEN8_MASTER_IRQ			_MMIO(0x44200)
4341 #define  GEN8_GT_RCS_IRQ		(1 << 0)
4343 #define XELPD_DISPLAY_ERR_FATAL_MASK	_MMIO(0x4421c)
4345 #define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
4346 #define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
4347 #define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
4348 #define GEN8_GT_IER(which) _MMIO(0x4430c + (0x10 * (which)))
4350 #define GEN8_RCS_IRQ_SHIFT 0
4352 #define GEN8_VCS0_IRQ_SHIFT 0  /* NB: VCS1 in bspec! */
4354 #define GEN8_VECS_IRQ_SHIFT 0
4357 #define GEN8_DE_PIPE_ISR(pipe) _MMIO(0x44400 + (0x10 * (pipe)))
4358 #define GEN8_DE_PIPE_IMR(pipe) _MMIO(0x44404 + (0x10 * (pipe)))
4359 #define GEN8_DE_PIPE_IIR(pipe) _MMIO(0x44408 + (0x10 * (pipe)))
4360 #define GEN8_DE_PIPE_IER(pipe) _MMIO(0x4440c + (0x10 * (pipe)))
4374 #define  GEN8_PIPE_VBLANK		(1 << 0)
4410 #define GEN8_DE_PORT_ISR _MMIO(0x44440)
4411 #define GEN8_DE_PORT_IMR _MMIO(0x44444)
4412 #define GEN8_DE_PORT_IIR _MMIO(0x44448)
4413 #define GEN8_DE_PORT_IER _MMIO(0x4444c)
4429 #define  GEN8_AUX_CHANNEL_A		(1 << 0)
4440 #define  TGL_DE_PORT_AUX_DDIA		REG_BIT(0)
4442 #define GEN8_DE_MISC_ISR _MMIO(0x44460)
4443 #define GEN8_DE_MISC_IMR _MMIO(0x44464)
4444 #define GEN8_DE_MISC_IIR _MMIO(0x44468)
4445 #define GEN8_DE_MISC_IER _MMIO(0x4446c)
4451 #define GEN8_PCU_ISR _MMIO(0x444e0)
4452 #define GEN8_PCU_IMR _MMIO(0x444e4)
4453 #define GEN8_PCU_IIR _MMIO(0x444e8)
4454 #define GEN8_PCU_IER _MMIO(0x444ec)
4456 #define GEN11_GU_MISC_ISR	_MMIO(0x444f0)
4457 #define GEN11_GU_MISC_IMR	_MMIO(0x444f4)
4458 #define GEN11_GU_MISC_IIR	_MMIO(0x444f8)
4459 #define GEN11_GU_MISC_IER	_MMIO(0x444fc)
4462 #define GEN11_GFX_MSTR_IRQ		_MMIO(0x190010)
4469 #define  GEN11_GT_DW0_IRQ		(1 << 0)
4471 #define DG1_MSTR_TILE_INTR		_MMIO(0x190008)
4475 #define GEN11_DISPLAY_INT_CTL		_MMIO(0x44200)
4486 #define GEN11_DE_HPD_ISR		_MMIO(0x44470)
4487 #define GEN11_DE_HPD_IMR		_MMIO(0x44474)
4488 #define GEN11_DE_HPD_IIR		_MMIO(0x44478)
4489 #define GEN11_DE_HPD_IER		_MMIO(0x4447c)
4505 #define GEN11_TBT_HOTPLUG_CTL				_MMIO(0x44030)
4506 #define GEN11_TC_HOTPLUG_CTL				_MMIO(0x44038)
4510 #define  GEN11_HOTPLUG_CTL_NO_DETECT(hpd_pin)		(0 << (_HPD_PIN_TC(hpd_pin) * 4))
4512 #define PICAINTERRUPT_ISR			_MMIO(0x16FE50)
4513 #define PICAINTERRUPT_IMR			_MMIO(0x16FE54)
4514 #define PICAINTERRUPT_IIR			_MMIO(0x16FE58)
4515 #define PICAINTERRUPT_IER			_MMIO(0x16FE5C)
4524 #define  XELPDP_TBT_HOTPLUG_MASK		REG_GENMASK(3, 0)
4526 #define XELPDP_PORT_HOTPLUG_CTL(hpd_pin)	_MMIO(0x16F270 + (_HPD_PIN_TC(hpd_pin) * 0x200))
4532 #define  XELPDP_DP_ALT_HPD_SHORT_DETECT		REG_BIT(0)
4534 #define XELPDP_INITIATE_PMDEMAND_REQUEST(dword)		_MMIO(0x45230 + 4 * (dword))
4540 #define  XELPDP_PMDEMAND_PHYS_MASK			REG_GENMASK(2, 0)
4546 #define  XELPDP_PMDEMAND_PLLS_MASK			REG_GENMASK(2, 0)
4548 #define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
4551 #define ILK_DISPLAY_CHICKEN2	_MMIO(0x42004)
4557 #define FUSE_STRAP		_MMIO(0x42014)
4568 #define FUSE_STRAP3		_MMIO(0x42020)
4571 #define ILK_DSPCLK_GATE_D	_MMIO(0x42020)
4578 #define IVB_CHICKEN3		_MMIO(0x4200c)
4582 #define CHICKEN_PAR1_1		_MMIO(0x42080)
4592 #define CHICKEN_PAR2_1		_MMIO(0x42090)
4595 #define CHICKEN_MISC_2		_MMIO(0x42084)
4603 #define CHICKEN_MISC_4		_MMIO(0x4208c)
4605 #define   CHICKEN_FBC_STRIDE_MASK	REG_GENMASK(12, 0)
4608 #define _CHICKEN_PIPESL_1_A	0x420b0
4609 #define _CHICKEN_PIPESL_1_B	0x420b4
4612 #define   HSW_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
4617 #define   HSW_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
4624 #define   SKL_PLANE1_STRETCH_MAX_MASK	REG_GENMASK(1, 0)
4625 #define   SKL_PLANE1_STRETCH_MAX_X8	REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
4629 #define   BDW_UNMASK_VBL_TO_REGS_IN_SRD	REG_BIT(0) /* bdw */
4631 #define _CHICKEN_TRANS_A	0x420c0
4632 #define _CHICKEN_TRANS_B	0x420c4
4633 #define _CHICKEN_TRANS_C	0x420c8
4634 #define _CHICKEN_TRANS_EDP	0x420cc
4635 #define _CHICKEN_TRANS_D	0x420d8
4642 #define _MTL_CHICKEN_TRANS_A	0x604e0
4643 #define _MTL_CHICKEN_TRANS_B	0x614e0
4661 #define DISP_ARB_CTL	_MMIO(0x45000)
4666 #define DISP_ARB_CTL2	_MMIO(0x45004)
4670 #define GEN7_MSG_CTL	_MMIO(0x45010)
4672 #define  WAIT_FOR_PCH_FLR_ACK		(1 << 0)
4674 #define _BW_BUDDY0_CTL			0x45130
4675 #define _BW_BUDDY1_CTL			0x45140
4683 #define _BW_BUDDY0_PAGE_MASK		0x45134
4684 #define _BW_BUDDY1_PAGE_MASK		0x45144
4689 #define HSW_NDE_RSTWRN_OPT	_MMIO(0x46408)
4693 #define GEN8_CHICKEN_DCPR_1			_MMIO(0x46430)
4704 #define GEN11_CHICKEN_DCPR_2			_MMIO(0x46434)
4710 #define XELPD_CHICKEN_DCPR_3			_MMIO(0x46438)
4713 #define SKL_DFSM			_MMIO(0x51000)
4717 #define   SKL_DFSM_CDCLK_LIMIT_675	(0 << 23)
4728 #define SKL_DSSM				_MMIO(0x51004)
4730 #define ICL_DSSM_CDCLK_PLL_REFCLK_24MHz		(0 << 29)
4734 #define GMD_ID_DISPLAY				_MMIO(0x510a0)
4737 #define   GMD_ID_STEP				REG_GENMASK(5, 0)
4740 #define _PIPEA_CHICKEN				0x70038
4741 #define _PIPEB_CHICKEN				0x71038
4742 #define _PIPEC_CHICKEN				0x72038
4753 #define PCH_DISPLAY_BASE	0xc0000u
4793 #define SDE_TRANSA_FIFO_UNDER	(1 << 0)
4794 #define SDE_TRANS_MASK		(0x3f)
4833 #define SDE_FDI_RXA_CPT		(1 << 0)
4861 #define SDEISR  _MMIO(0xc4000)
4862 #define SDEIMR  _MMIO(0xc4004)
4863 #define SDEIIR  _MMIO(0xc4008)
4864 #define SDEIER  _MMIO(0xc400c)
4866 #define SERR_INT			_MMIO(0xc4040)
4871 #define PCH_PORT_HOTPLUG		_MMIO(0xc4030)	/* SHOTPLUG_CTL */
4875 #define  PORTA_HOTPLUG_NO_DETECT	(0 << 24) /* SPT+ & BXT */
4879 #define  PORTD_PULSE_DURATION_2ms	(0 << 18) /* pre-LPT */
4885 #define  PORTD_HOTPLUG_NO_DETECT	(0 << 16)
4890 #define  PORTC_PULSE_DURATION_2ms	(0 << 10) /* pre-LPT */
4896 #define  PORTC_HOTPLUG_NO_DETECT	(0 << 8)
4901 #define  PORTB_PULSE_DURATION_2ms	(0 << 2) /* pre-LPT */
4906 #define  PORTB_HOTPLUG_STATUS_MASK	(3 << 0)
4907 #define  PORTB_HOTPLUG_NO_DETECT	(0 << 0)
4908 #define  PORTB_HOTPLUG_SHORT_DETECT	(1 << 0)
4909 #define  PORTB_HOTPLUG_LONG_DETECT	(2 << 0)
4914 #define PCH_PORT_HOTPLUG2		_MMIO(0xc403C)	/* SHOTPLUG_CTL2 SPT+ */
4916 #define  PORTE_HOTPLUG_STATUS_MASK	(3 << 0)
4917 #define  PORTE_HOTPLUG_NO_DETECT	(0 << 0)
4918 #define  PORTE_HOTPLUG_SHORT_DETECT	(1 << 0)
4919 #define  PORTE_HOTPLUG_LONG_DETECT	(2 << 0)
4926 #define SHOTPLUG_CTL_DDI				_MMIO(0xc4030)
4927 #define   SHOTPLUG_CTL_DDI_HPD_ENABLE(hpd_pin)			(0x8 << (_HPD_PIN_DDI(hpd_pin) * 4))
4928 #define   SHOTPLUG_CTL_DDI_HPD_OUTPUT_DATA(hpd_pin)		(0x4 << (_HPD_PIN_DDI(hpd_pin) * 4))
4929 #define   SHOTPLUG_CTL_DDI_HPD_STATUS_MASK(hpd_pin)		(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
4930 #define   SHOTPLUG_CTL_DDI_HPD_NO_DETECT(hpd_pin)		(0x0 << (_HPD_PIN_DDI(hpd_pin) * 4))
4931 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_DETECT(hpd_pin)		(0x1 << (_HPD_PIN_DDI(hpd_pin) * 4))
4932 #define   SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(hpd_pin)		(0x2 << (_HPD_PIN_DDI(hpd_pin) * 4))
4933 #define   SHOTPLUG_CTL_DDI_HPD_SHORT_LONG_DETECT(hpd_pin)	(0x3 << (_HPD_PIN_DDI(hpd_pin) * 4))
4935 #define SHOTPLUG_CTL_TC				_MMIO(0xc4034)
4940 #define SHPD_FILTER_CNT				_MMIO(0xc4038)
4941 #define   SHPD_FILTER_CNT_500_ADJ		0x001D9
4942 #define   SHPD_FILTER_CNT_250			0x000F8
4944 #define _PCH_DPLL_A              0xc6014
4945 #define _PCH_DPLL_B              0xc6018
4946 #define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
4948 #define _PCH_FPA0                0xc6040
4949 #define  FP_CB_TUNE		(0x3 << 22)
4950 #define _PCH_FPA1                0xc6044
4951 #define _PCH_FPB0                0xc6048
4952 #define _PCH_FPB1                0xc604c
4953 #define PCH_FP0(pll) _MMIO((pll) == 0 ? _PCH_FPA0 : _PCH_FPB0)
4954 #define PCH_FP1(pll) _MMIO((pll) == 0 ? _PCH_FPA1 : _PCH_FPB1)
4956 #define PCH_DPLL_TEST           _MMIO(0xc606c)
4958 #define PCH_DREF_CONTROL        _MMIO(0xC6200)
4959 #define  DREF_CONTROL_MASK      0x7fc3
4960 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0 << 13)
4964 #define  DREF_SSC_SOURCE_DISABLE                (0 << 11)
4967 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0 << 9)
4971 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0 << 7)
4974 #define  DREF_SSC4_DOWNSPREAD                   (0 << 6)
4976 #define  DREF_SSC1_DISABLE                      (0 << 1)
4978 #define  DREF_SSC4_DISABLE                      (0)
4981 #define PCH_RAWCLK_FREQ         _MMIO(0xc6204)
4986 #define  RAWCLK_FREQ_MASK       0x3ff
4987 #define  CNP_RAWCLK_DIV_MASK	(0x3ff << 16)
4989 #define  CNP_RAWCLK_FRAC_MASK	(0xf << 26)
4993 #define PCH_DPLL_TMR_CFG        _MMIO(0xc6208)
4995 #define PCH_SSC4_PARMS          _MMIO(0xc6210)
4996 #define PCH_SSC4_AUX_PARMS      _MMIO(0xc6214)
4998 #define PCH_DPLL_SEL		_MMIO(0xc7000)
5000 #define	 TRANS_DPLLA_SEL(pipe)		0
5005 #define _PCH_TRANS_HTOTAL_A		0xe0000
5007 #define  TRANS_HACTIVE_SHIFT		0
5008 #define _PCH_TRANS_HBLANK_A		0xe0004
5010 #define  TRANS_HBLANK_START_SHIFT	0
5011 #define _PCH_TRANS_HSYNC_A		0xe0008
5013 #define  TRANS_HSYNC_START_SHIFT	0
5014 #define _PCH_TRANS_VTOTAL_A		0xe000c
5016 #define  TRANS_VACTIVE_SHIFT		0
5017 #define _PCH_TRANS_VBLANK_A		0xe0010
5019 #define  TRANS_VBLANK_START_SHIFT	0
5020 #define _PCH_TRANS_VSYNC_A		0xe0014
5022 #define  TRANS_VSYNC_START_SHIFT	0
5023 #define _PCH_TRANS_VSYNCSHIFT_A		0xe0028
5025 #define _PCH_TRANSA_DATA_M1	0xe0030
5026 #define _PCH_TRANSA_DATA_N1	0xe0034
5027 #define _PCH_TRANSA_DATA_M2	0xe0038
5028 #define _PCH_TRANSA_DATA_N2	0xe003c
5029 #define _PCH_TRANSA_LINK_M1	0xe0040
5030 #define _PCH_TRANSA_LINK_N1	0xe0044
5031 #define _PCH_TRANSA_LINK_M2	0xe0048
5032 #define _PCH_TRANSA_LINK_N2	0xe004c
5035 #define _VIDEO_DIP_CTL_A         0xe0200
5036 #define _VIDEO_DIP_DATA_A        0xe0208
5037 #define _VIDEO_DIP_GCP_A         0xe0210
5040 #define  GCP_AV_MUTE			(1 << 0)
5042 #define _VIDEO_DIP_CTL_B         0xe1200
5043 #define _VIDEO_DIP_DATA_B        0xe1208
5044 #define _VIDEO_DIP_GCP_B         0xe1210
5051 #define _VLV_VIDEO_DIP_CTL_A		(VLV_DISPLAY_BASE + 0x60200)
5052 #define _VLV_VIDEO_DIP_DATA_A		(VLV_DISPLAY_BASE + 0x60208)
5053 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A	(VLV_DISPLAY_BASE + 0x60210)
5055 #define _VLV_VIDEO_DIP_CTL_B		(VLV_DISPLAY_BASE + 0x61170)
5056 #define _VLV_VIDEO_DIP_DATA_B		(VLV_DISPLAY_BASE + 0x61174)
5057 #define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B	(VLV_DISPLAY_BASE + 0x61178)
5059 #define _CHV_VIDEO_DIP_CTL_C		(VLV_DISPLAY_BASE + 0x611f0)
5060 #define _CHV_VIDEO_DIP_DATA_C		(VLV_DISPLAY_BASE + 0x611f4)
5061 #define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C	(VLV_DISPLAY_BASE + 0x611f8)
5075 #define _HSW_VIDEO_DIP_CTL_A		0x60200
5076 #define _HSW_VIDEO_DIP_AVI_DATA_A	0x60220
5077 #define _HSW_VIDEO_DIP_VS_DATA_A	0x60260
5078 #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
5079 #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
5080 #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
5081 #define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
5082 #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
5083 #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
5084 #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
5085 #define _HSW_VIDEO_DIP_GMP_ECC_A	0x60300
5086 #define _HSW_VIDEO_DIP_VSC_ECC_A	0x60344
5087 #define _HSW_VIDEO_DIP_GCP_A		0x60210
5089 #define _HSW_VIDEO_DIP_CTL_B		0x61200
5090 #define _HSW_VIDEO_DIP_AVI_DATA_B	0x61220
5091 #define _HSW_VIDEO_DIP_VS_DATA_B	0x61260
5092 #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
5093 #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
5094 #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
5095 #define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
5096 #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
5097 #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
5098 #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
5099 #define _HSW_VIDEO_DIP_GMP_ECC_B	0x61300
5100 #define _HSW_VIDEO_DIP_VSC_ECC_B	0x61344
5101 #define _HSW_VIDEO_DIP_GCP_B		0x61210
5109 #define _ICL_VIDEO_DIP_PPS_DATA_A	0x60350
5110 #define _ICL_VIDEO_DIP_PPS_DATA_B	0x61350
5111 #define _ICL_VIDEO_DIP_PPS_ECC_A	0x603D4
5112 #define _ICL_VIDEO_DIP_PPS_ECC_B	0x613D4
5125 #define _HSW_STEREO_3D_CTL_A		0x70020
5127 #define _HSW_STEREO_3D_CTL_B		0x71020
5131 #define _PCH_TRANS_HTOTAL_B          0xe1000
5132 #define _PCH_TRANS_HBLANK_B          0xe1004
5133 #define _PCH_TRANS_HSYNC_B           0xe1008
5134 #define _PCH_TRANS_VTOTAL_B          0xe100c
5135 #define _PCH_TRANS_VBLANK_B          0xe1010
5136 #define _PCH_TRANS_VSYNC_B           0xe1014
5137 #define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
5147 #define _PCH_TRANSB_DATA_M1	0xe1030
5148 #define _PCH_TRANSB_DATA_N1	0xe1034
5149 #define _PCH_TRANSB_DATA_M2	0xe1038
5150 #define _PCH_TRANSB_DATA_N2	0xe103c
5151 #define _PCH_TRANSB_LINK_M1	0xe1040
5152 #define _PCH_TRANSB_LINK_N1	0xe1044
5153 #define _PCH_TRANSB_LINK_M2	0xe1048
5154 #define _PCH_TRANSB_LINK_N2	0xe104c
5165 #define _PCH_TRANSACONF              0xf0008
5166 #define _PCH_TRANSBCONF              0xf1008
5172 #define  TRANS_FRAME_START_DELAY(x)	REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
5174 #define  TRANS_INTERLACE_PROGRESSIVE	REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
5178 #define  TRANS_BPC_8			REG_FIELD_PREP(TRANS_BPC_MASK, 0)
5183 #define _TRANSA_CHICKEN1	 0xf0060
5184 #define _TRANSB_CHICKEN1	 0xf1060
5189 #define _TRANSA_CHICKEN2	 0xf0064
5190 #define _TRANSB_CHICKEN2	 0xf1064
5195 …CHICKEN2_FRAME_START_DELAY(x)		REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
5199 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
5215 #define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf << 8)
5219 #define  SPT_PWM_GRANULARITY		(1 << 0)
5220 #define SOUTH_CHICKEN2		_MMIO(0xc2004)
5224 #define  DPLS_EDP_PPS_FIX_DIS		(1 << 0)
5226 #define SOUTH_DSPCLK_GATE_D	_MMIO(0xc2020)
5235 #define _PCH_DP_B		0xe4100
5237 #define _PCH_DPB_AUX_CH_CTL	0xe4110
5238 #define _PCH_DPB_AUX_CH_DATA1	0xe4114
5239 #define _PCH_DPB_AUX_CH_DATA2	0xe4118
5240 #define _PCH_DPB_AUX_CH_DATA3	0xe411c
5241 #define _PCH_DPB_AUX_CH_DATA4	0xe4120
5242 #define _PCH_DPB_AUX_CH_DATA5	0xe4124
5244 #define _PCH_DP_C		0xe4200
5246 #define _PCH_DPC_AUX_CH_CTL	0xe4210
5247 #define _PCH_DPC_AUX_CH_DATA1	0xe4214
5248 #define _PCH_DPC_AUX_CH_DATA2	0xe4218
5249 #define _PCH_DPC_AUX_CH_DATA3	0xe421c
5250 #define _PCH_DPC_AUX_CH_DATA4	0xe4220
5251 #define _PCH_DPC_AUX_CH_DATA5	0xe4224
5253 #define _PCH_DP_D		0xe4300
5255 #define _PCH_DPD_AUX_CH_CTL	0xe4310
5256 #define _PCH_DPD_AUX_CH_DATA1	0xe4314
5257 #define _PCH_DPD_AUX_CH_DATA2	0xe4318
5258 #define _PCH_DPD_AUX_CH_DATA3	0xe431c
5259 #define _PCH_DPD_AUX_CH_DATA4	0xe4320
5260 #define _PCH_DPD_AUX_CH_DATA5	0xe4324
5266 #define _TRANS_DP_CTL_A		0xe0300
5267 #define _TRANS_DP_CTL_B		0xe1300
5268 #define _TRANS_DP_CTL_C		0xe2300
5277 #define  TRANS_DP_BPC_8			REG_FIELD_PREP(TRANS_DP_BPC_MASK, 0)
5284 #define _TRANS_DP2_CTL_A			0x600a0
5285 #define _TRANS_DP2_CTL_B			0x610a0
5286 #define _TRANS_DP2_CTL_C			0x620a0
5287 #define _TRANS_DP2_CTL_D			0x630a0
5293 #define _TRANS_DP2_VFREQHIGH_A			0x600a4
5294 #define _TRANS_DP2_VFREQHIGH_B			0x610a4
5295 #define _TRANS_DP2_VFREQHIGH_C			0x620a4
5296 #define _TRANS_DP2_VFREQHIGH_D			0x630a4
5301 #define _TRANS_DP2_VFREQLOW_A			0x600a8
5302 #define _TRANS_DP2_VFREQLOW_B			0x610a8
5303 #define _TRANS_DP2_VFREQLOW_C			0x620a8
5304 #define _TRANS_DP2_VFREQLOW_D			0x630a8
5309 #define  EDP_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
5310 #define  EDP_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
5311 #define  EDP_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
5312 #define  EDP_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
5314 #define  EDP_LINK_TRAIN_400_600MV_0DB_SNB_B	(0x0 << 22)
5315 #define  EDP_LINK_TRAIN_400MV_3_5DB_SNB_B	(0x1 << 22)
5316 #define  EDP_LINK_TRAIN_400_600MV_6DB_SNB_B	(0x3a << 22)
5317 #define  EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B	(0x39 << 22)
5318 #define  EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B	(0x38 << 22)
5319 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_SNB	(0x3f << 22)
5322 #define EDP_LINK_TRAIN_400MV_0DB_IVB		(0x24 << 22)
5323 #define EDP_LINK_TRAIN_400MV_3_5DB_IVB		(0x2a << 22)
5324 #define EDP_LINK_TRAIN_400MV_6DB_IVB		(0x2f << 22)
5325 #define EDP_LINK_TRAIN_600MV_0DB_IVB		(0x30 << 22)
5326 #define EDP_LINK_TRAIN_600MV_3_5DB_IVB		(0x36 << 22)
5327 #define EDP_LINK_TRAIN_800MV_0DB_IVB		(0x38 << 22)
5328 #define EDP_LINK_TRAIN_800MV_3_5DB_IVB		(0x3e << 22)
5331 #define EDP_LINK_TRAIN_500MV_0DB_IVB		(0x00 << 22)
5332 #define EDP_LINK_TRAIN_1000MV_0DB_IVB		(0x20 << 22)
5333 #define EDP_LINK_TRAIN_500MV_3_5DB_IVB		(0x02 << 22)
5334 #define EDP_LINK_TRAIN_1000MV_3_5DB_IVB		(0x22 << 22)
5335 #define EDP_LINK_TRAIN_1000MV_6DB_IVB		(0x23 << 22)
5337 #define  EDP_LINK_TRAIN_VOL_EMP_MASK_IVB	(0x3f << 22)
5339 #define  VLV_PMWGICZ				_MMIO(0x1300a4)
5341 #define  HSW_EDRAM_CAP				_MMIO(0x120010)
5342 #define    EDRAM_ENABLED			0x1
5343 #define    EDRAM_NUM_BANKS(cap)			(((cap) >> 1) & 0xf)
5344 #define    EDRAM_WAYS_IDX(cap)			(((cap) >> 5) & 0x7)
5345 #define    EDRAM_SETS_IDX(cap)			(((cap) >> 8) & 0x3)
5347 #define VLV_CHICKEN_3				_MMIO(VLV_DISPLAY_BASE + 0x7040C)
5351 #define GEN6_PCODE_MAILBOX			_MMIO(0x138124)
5355 #define   GEN6_PCODE_MB_COMMAND			REG_GENMASK(7, 0)
5356 #define   GEN6_PCODE_ERROR_MASK			0xFF
5357 #define     GEN6_PCODE_SUCCESS			0x0
5358 #define     GEN6_PCODE_ILLEGAL_CMD		0x1
5359 #define     GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
5360 #define     GEN6_PCODE_TIMEOUT			0x3
5361 #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
5362 #define     GEN7_PCODE_TIMEOUT			0x2
5363 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
5364 #define     GEN11_PCODE_ILLEGAL_SUBCOMMAND	0x4
5365 #define     GEN11_PCODE_LOCKED			0x6
5366 #define     GEN11_PCODE_REJECTED		0x11
5367 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
5368 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
5369 #define   GEN6_PCODE_READ_RC6VIDS		0x5
5372 #define   BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ	0x18
5373 #define   GEN9_PCODE_READ_MEM_LATENCY		0x6
5377 #define     GEN9_MEM_LATENCY_LEVEL_0_4_MASK	REG_GENMASK(7, 0)
5378 #define   SKL_PCODE_LOAD_HDCP_KEYS		0x5
5379 #define   SKL_PCODE_CDCLK_CONTROL		0x7
5380 #define     SKL_CDCLK_PREPARE_FOR_CHANGE	0x3
5381 #define     SKL_CDCLK_READY_FOR_CHANGE		0x1
5382 #define   GEN6_PCODE_WRITE_MIN_FREQ_TABLE	0x8
5383 #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
5384 #define   GEN6_READ_OC_PARAMS			0xc
5385 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
5386 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
5387 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
5388 #define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO	((0) | (0x2 << 8))
5389 #define   DISPLAY_TO_PCODE_CDCLK_MAX		0x28D
5390 #define   DISPLAY_TO_PCODE_VOLTAGE_MASK		REG_GENMASK(1, 0)
5403 #define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
5404 #define     ICL_PCODE_REP_QGV_MASK		REG_GENMASK(1, 0)
5405 #define     ICL_PCODE_REP_QGV_SAFE		REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
5409 #define     ADLS_PCODE_REP_PSF_SAFE		REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
5412 #define     ICL_PCODE_REQ_QGV_PT_MASK		REG_GENMASK(7, 0)
5416 #define   GEN6_PCODE_READ_D_COMP		0x10
5417 #define   GEN6_PCODE_WRITE_D_COMP		0x11
5418 #define   ICL_PCODE_EXIT_TCCOLD			0x12
5419 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
5420 #define   DISPLAY_IPS_CONTROL			0x19
5421 #define   TGL_PCODE_TCCOLD			0x26
5422 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED	REG_BIT(0)
5423 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ	0
5424 #define     TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ	REG_BIT(0)
5427 #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL	0x1A
5428 #define   GEN9_PCODE_SAGV_CONTROL		0x21
5429 #define     GEN9_SAGV_DISABLE			0x0
5430 #define     GEN9_SAGV_IS_DISABLED		0x1
5431 #define     GEN9_SAGV_ENABLE			0x3
5432 #define   DG1_PCODE_STATUS			0x7E
5433 #define     DG1_UNCORE_GET_INIT_STATUS		0x0
5434 #define     DG1_UNCORE_INIT_STATUS_COMPLETE	0x1
5435 #define   PCODE_POWER_SETUP			0x7C
5436 #define     POWER_SETUP_SUBCOMMAND_READ_I1	0x4
5437 #define     POWER_SETUP_SUBCOMMAND_WRITE_I1	0x5
5440 #define	    POWER_SETUP_I1_DATA_MASK		REG_GENMASK(15, 0)
5441 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
5442 #define   XEHP_PCODE_FREQUENCY_CONFIG		0x6e	/* xehpsdv, pvc */
5444 #define     PCODE_MBOX_FC_SC_READ_FUSED_P0	0x0
5445 #define     PCODE_MBOX_FC_SC_READ_FUSED_PN	0x1
5448 #define     PCODE_MBOX_DOMAIN_NONE		0x0
5449 #define     PCODE_MBOX_DOMAIN_MEDIAFF		0x3
5450 #define GEN6_PCODE_DATA				_MMIO(0x138128)
5453 #define GEN6_PCODE_DATA1			_MMIO(0x13812C)
5456 #define GEN7_L3CDERRST1(slice)		_MMIO(0xB008 + (slice) * 0x200) /* L3CD Error Status 1 */
5457 #define   GEN7_L3CDERRST1_ROW_MASK	(0x7ff << 14)
5473 #define GEN7_SO_WRITE_OFFSET(n)		_MMIO(0x5280 + (n) * 4)
5490 #define HSW_PWR_WELL_CTL1			_MMIO(0x45400)
5491 #define HSW_PWR_WELL_CTL2			_MMIO(0x45404)
5492 #define HSW_PWR_WELL_CTL3			_MMIO(0x45408)
5493 #define HSW_PWR_WELL_CTL4			_MMIO(0x4540C)
5494 #define   HSW_PWR_WELL_CTL_REQ(pw_idx)		(0x2 << ((pw_idx) * 2))
5495 #define   HSW_PWR_WELL_CTL_STATE(pw_idx)	(0x1 << ((pw_idx) * 2))
5511 #define   SKL_PW_CTL_IDX_MISC_IO		0
5518 #define   ICL_PW_CTL_IDX_PW_1			0
5526 #define ICL_PWR_WELL_CTL_AUX1			_MMIO(0x45440)
5527 #define ICL_PWR_WELL_CTL_AUX2			_MMIO(0x45444)
5528 #define ICL_PWR_WELL_CTL_AUX4			_MMIO(0x4544C)
5552 #define   ICL_PW_CTL_IDX_AUX_A			0
5554 #define ICL_PWR_WELL_CTL_DDI1			_MMIO(0x45450)
5555 #define ICL_PWR_WELL_CTL_DDI2			_MMIO(0x45454)
5556 #define ICL_PWR_WELL_CTL_DDI4			_MMIO(0x4545C)
5570 #define   ICL_PW_CTL_IDX_DDI_A			0
5573 #define HSW_PWR_WELL_CTL5			_MMIO(0x45410)
5577 #define HSW_PWR_WELL_CTL6			_MMIO(0x45414)
5588 #define SKL_FUSE_STATUS				_MMIO(0x42000)
5605 #define _ICL_AUX_ANAOVRD1_A		0x162398
5606 #define _ICL_AUX_ANAOVRD1_B		0x6C398
5611 #define   ICL_AUX_ANAOVRD1_ENABLE	(1 << 0)
5614 #define _TRANS_DDI_FUNC_CTL_A		0x60400
5615 #define _TRANS_DDI_FUNC_CTL_B		0x61400
5616 #define _TRANS_DDI_FUNC_CTL_C		0x62400
5617 #define _TRANS_DDI_FUNC_CTL_D		0x63400
5618 #define _TRANS_DDI_FUNC_CTL_EDP		0x6F400
5619 #define _TRANS_DDI_FUNC_CTL_DSI0	0x6b400
5620 #define _TRANS_DDI_FUNC_CTL_DSI1	0x6bc00
5628 #define  TGL_TRANS_DDI_PORT_MASK	(0xf << TGL_TRANS_DDI_PORT_SHIFT)
5632 #define  TRANS_DDI_MODE_SELECT_HDMI	(0 << 24)
5638 #define  TRANS_DDI_BPC_8		(0 << 20)
5648 #define  TRANS_DDI_EDP_INPUT_A_ON	(0 << 12)
5665 #define  TRANS_DDI_HDMI_SCRAMBLING	(1 << 0)
5670 #define _TRANS_DDI_FUNC_CTL2_A		0x60404
5671 #define _TRANS_DDI_FUNC_CTL2_B		0x61404
5672 #define _TRANS_DDI_FUNC_CTL2_C		0x62404
5673 #define _TRANS_DDI_FUNC_CTL2_EDP	0x6f404
5674 #define _TRANS_DDI_FUNC_CTL2_DSI0	0x6b404
5675 #define _TRANS_DDI_FUNC_CTL2_DSI1	0x6bc04
5678 #define  PORT_SYNC_MODE_MASTER_SELECT_MASK	REG_GENMASK(2, 0)
5681 #define TRANS_CMTG_CHICKEN		_MMIO(0x6fa90)
5685 #define _DP_TP_CTL_A			0x64040
5686 #define _DP_TP_CTL_B			0x64140
5687 #define _TGL_DP_TP_CTL_A		0x60540
5692 #define  DP_TP_CTL_MODE_SST			(0 << 27)
5698 #define  DP_TP_CTL_LINK_TRAIN_PAT1		(0 << 8)
5707 #define _DP_TP_STATUS_A			0x64044
5708 #define _DP_TP_STATUS_B			0x64144
5709 #define _TGL_DP_TP_STATUS_A		0x60544
5719 #define  DP_TP_STATUS_PAYLOAD_MAPPING_VC0	(3 << 0)
5722 #define _DDI_BUF_CTL_A				0x64000
5723 #define _DDI_BUF_CTL_B				0x64100
5728 #define  DDI_BUF_EMP_MASK			(0xf << 24)
5731 #define  DDI_BUF_PORT_DATA_10BIT		REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0)
5741 #define  DDI_INIT_DISPLAY_DETECTED		(1 << 0)
5744 #define _DDI_BUF_TRANS_A		0x64E00
5745 #define _DDI_BUF_TRANS_B		0x64E60
5751 #define _DDI_DP_COMP_CTL_A			0x605F0
5752 #define _DDI_DP_COMP_CTL_B			0x615F0
5755 #define   DDI_DP_COMP_CTL_D10_2			(0 << 28)
5761 #define   DDI_DP_COMP_CTL_HBR2_RESET		(0xFC << 0)
5764 #define _DDI_DP_COMP_PAT_A			0x605F4
5765 #define _DDI_DP_COMP_PAT_B			0x615F4
5771 #define SBI_ADDR			_MMIO(0xC6000)
5772 #define SBI_DATA			_MMIO(0xC6004)
5773 #define SBI_CTL_STAT			_MMIO(0xC6008)
5774 #define  SBI_CTL_DEST_ICLK		(0x0 << 16)
5775 #define  SBI_CTL_DEST_MPHY		(0x1 << 16)
5776 #define  SBI_CTL_OP_IORD		(0x2 << 8)
5777 #define  SBI_CTL_OP_IOWR		(0x3 << 8)
5778 #define  SBI_CTL_OP_CRRD		(0x6 << 8)
5779 #define  SBI_CTL_OP_CRWR		(0x7 << 8)
5780 #define  SBI_RESPONSE_FAIL		(0x1 << 1)
5781 #define  SBI_RESPONSE_SUCCESS		(0x0 << 1)
5782 #define  SBI_BUSY			(0x1 << 0)
5783 #define  SBI_READY			(0x0 << 0)
5786 #define  SBI_SSCDIVINTPHASE			0x0200
5787 #define  SBI_SSCDIVINTPHASE6			0x0600
5789 #define   SBI_SSCDIVINTPHASE_DIVSEL_MASK	(0x7f << 1)
5792 #define   SBI_SSCDIVINTPHASE_INCVAL_MASK	(0x7f << 8)
5795 #define   SBI_SSCDIVINTPHASE_PROPAGATE		(1 << 0)
5796 #define  SBI_SSCDITHPHASE			0x0204
5797 #define  SBI_SSCCTL				0x020c
5798 #define  SBI_SSCCTL6				0x060C
5800 #define   SBI_SSCCTL_DISABLE			(1 << 0)
5801 #define  SBI_SSCAUXDIV6				0x0610
5805 #define  SBI_DBUFF0				0x2a00
5806 #define  SBI_GEN0				0x1f00
5807 #define   SBI_GEN0_CFG_BUFFENABLE_DISABLE	(1 << 0)
5810 #define PIXCLK_GATE			_MMIO(0xC6020)
5811 #define  PIXCLK_GATE_UNGATE		(1 << 0)
5812 #define  PIXCLK_GATE_GATE		(0 << 0)
5815 #define SPLL_CTL			_MMIO(0x46020)
5817 #define  SPLL_REF_BCLK			(0 << 28)
5823 #define  SPLL_FREQ_810MHz		(0 << 26)
5829 #define _WRPLL_CTL1			0x46040
5830 #define _WRPLL_CTL2			0x46060
5833 #define  WRPLL_REF_BCLK			(0 << 28)
5840 #define  WRPLL_DIVIDER_REFERENCE(x)	((x) << 0)
5841 #define  WRPLL_DIVIDER_REF_MASK		(0xff)
5843 #define  WRPLL_DIVIDER_POST_MASK	(0x3f << 8)
5847 #define  WRPLL_DIVIDER_FB_MASK		(0xff << 16)
5850 #define _PORT_CLK_SEL_A			0x46100
5851 #define _PORT_CLK_SEL_B			0x46104
5854 #define  PORT_CLK_SEL_LCPLL_2700	REG_FIELD_PREP(PORT_CLK_SEL_MASK, 0)
5866 #define  DDI_CLK_SEL_NONE		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x0)
5867 #define  DDI_CLK_SEL_MG			REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0x8)
5868 #define  DDI_CLK_SEL_TBT_162		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xC)
5869 #define  DDI_CLK_SEL_TBT_270		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xD)
5870 #define  DDI_CLK_SEL_TBT_540		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xE)
5871 #define  DDI_CLK_SEL_TBT_810		REG_FIELD_PREP(DDI_CLK_SEL_MASK, 0xF)
5874 #define _TRANS_CLK_SEL_A		0x46140
5875 #define _TRANS_CLK_SEL_B		0x46144
5878 #define  TRANS_CLK_SEL_DISABLED		(0x0 << 29)
5880 #define  TGL_TRANS_CLK_SEL_DISABLED	(0x0 << 28)
5884 #define CDCLK_FREQ			_MMIO(0x46200)
5886 #define _TRANSA_MSA_MISC		0x60410
5887 #define _TRANSB_MSA_MISC		0x61410
5888 #define _TRANSC_MSA_MISC		0x62410
5889 #define _TRANS_EDP_MSA_MISC		0x6f410
5893 #define _TRANS_A_SET_CONTEXT_LATENCY		0x6007C
5894 #define _TRANS_B_SET_CONTEXT_LATENCY		0x6107C
5895 #define _TRANS_C_SET_CONTEXT_LATENCY		0x6207C
5896 #define _TRANS_D_SET_CONTEXT_LATENCY		0x6307C
5898 #define  TRANS_SET_CONTEXT_LATENCY_MASK		REG_GENMASK(15, 0)
5902 #define LCPLL_CTL			_MMIO(0x130040)
5905 #define  LCPLL_REF_NON_SSC		(0 << 28)
5910 #define  LCPLL_CLK_FREQ_450		(0 << 26)
5926 #define CDCLK_CTL			_MMIO(0x46000)
5928 #define  CDCLK_FREQ_450_432		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)
5933 #define  BXT_CDCLK_CD2X_DIV_SEL_1	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
5940 #define  ICL_CDCLK_CD2X_PIPE(pipe)	(_PICK(pipe, 0, 2, 6) << 19)
5945 #define  CDCLK_FREQ_DECIMAL_MASK	(0x7ff)
5948 #define CDCLK_SQUASH_CTL		_MMIO(0x46008)
5952 #define  CDCLK_SQUASH_WAVEFORM_MASK	REG_GENMASK(15, 0)
5956 #define LCPLL1_CTL		_MMIO(0x46010)
5957 #define LCPLL2_CTL		_MMIO(0x46014)
5961 #define DPLL_CTRL1		_MMIO(0x6C058)
5968 #define  DPLL_CTRL1_LINK_RATE_2700		0
5976 #define DPLL_CTRL2				_MMIO(0x6C05C)
5984 #define DPLL_STATUS	_MMIO(0x6C060)
5988 #define _DPLL1_CFGCR1	0x6C040
5989 #define _DPLL2_CFGCR1	0x6C048
5990 #define _DPLL3_CFGCR1	0x6C050
5992 #define  DPLL_CFGCR1_DCO_FRACTION_MASK	(0x7fff << 9)
5994 #define  DPLL_CFGCR1_DCO_INTEGER_MASK	(0x1ff)
5996 #define _DPLL1_CFGCR2	0x6C044
5997 #define _DPLL2_CFGCR2	0x6C04C
5998 #define _DPLL3_CFGCR2	0x6C054
5999 #define  DPLL_CFGCR2_QDIV_RATIO_MASK	(0xff << 8)
6004 #define  DPLL_CFGCR2_KDIV_5 (0 << 5)
6010 #define  DPLL_CFGCR2_PDIV_1 (0 << 2)
6021 #define ICL_DPCLKA_CFGCR0			_MMIO(0x164280)
6030 #define  RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy)	_PICK(phy, 0, 2, 4, 27)
6042 #define _DG1_DPCLKA_CFGCR0				0x164280
6043 #define _DG1_DPCLKA1_CFGCR0				0x16C280
6052 #define   DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy)	(0x3 << DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy))
6055 #define _ADLS_DPCLKA_CFGCR0			0x164280
6056 #define _ADLS_DPCLKA_CFGCR1			0x1642BC
6064 #define  ADLS_DPCLKA_DDIA_SEL_MASK			REG_GENMASK(1, 0)
6067 #define  ADLS_DPCLKA_DDIJ_SEL_MASK			REG_GENMASK(1, 0)
6076 #define _DPLL0_ENABLE		0x46010
6077 #define _DPLL1_ENABLE		0x46014
6078 #define _ADLS_DPLL2_ENABLE	0x46018
6079 #define _ADLS_DPLL3_ENABLE	0x46030
6088 #define _DG2_PLL3_ENABLE	0x4601C
6094 #define TBT_PLL_ENABLE		_MMIO(0x46020)
6096 #define _MG_PLL1_ENABLE		0x46030
6097 #define _MG_PLL2_ENABLE		0x46034
6098 #define _MG_PLL3_ENABLE		0x46038
6099 #define _MG_PLL4_ENABLE		0x4603C
6110 #define PORTTC1_PLL_ENABLE	0x46038
6111 #define PORTTC2_PLL_ENABLE	0x46040
6117 #define _ICL_DPLL0_CFGCR0		0x164000
6118 #define _ICL_DPLL1_CFGCR0		0x164080
6124 #define   DPLL_CFGCR0_LINK_RATE_MASK	(0xf << 25)
6125 #define   DPLL_CFGCR0_LINK_RATE_2700	(0 << 25)
6133 #define   DPLL_CFGCR0_DCO_FRACTION_MASK	(0x7fff << 10)
6136 #define   DPLL_CFGCR0_DCO_INTEGER_MASK	(0x3ff)
6138 #define _ICL_DPLL0_CFGCR1		0x164004
6139 #define _ICL_DPLL1_CFGCR1		0x164084
6142 #define   DPLL_CFGCR1_QDIV_RATIO_MASK	(0xff << 10)
6153 #define   DPLL_CFGCR1_PDIV_MASK		(0xf << 2)
6160 #define   DPLL_CFGCR1_CENTRAL_FREQ	(3 << 0)
6161 #define   DPLL_CFGCR1_CENTRAL_FREQ_8400	(3 << 0)
6162 #define   TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL	(0 << 0)
6164 #define _TGL_DPLL0_CFGCR0		0x164284
6165 #define _TGL_DPLL1_CFGCR0		0x16428C
6166 #define _TGL_TBTPLL_CFGCR0		0x16429C
6173 #define _TGL_DPLL0_DIV0					0x164B00
6174 #define _TGL_DPLL1_DIV0					0x164C00
6179 #define _TGL_DPLL0_CFGCR1		0x164288
6180 #define _TGL_DPLL1_CFGCR1		0x164290
6181 #define _TGL_TBTPLL_CFGCR1		0x1642A0
6188 #define _DG1_DPLL2_CFGCR0		0x16C284
6189 #define _DG1_DPLL3_CFGCR0		0x16C28C
6194 #define _DG1_DPLL2_CFGCR1               0x16C288
6195 #define _DG1_DPLL3_CFGCR1               0x16C290
6201 #define _ADLS_DPLL4_CFGCR0		0x164294
6202 #define _ADLS_DPLL3_CFGCR0		0x1642C0
6207 #define _ADLS_DPLL4_CFGCR1		0x164298
6208 #define _ADLS_DPLL3_CFGCR1		0x1642C4
6214 #define BXT_DE_PLL_CTL			_MMIO(0x6d000)
6216 #define   BXT_DE_PLL_RATIO_MASK		0xff
6218 #define BXT_DE_PLL_ENABLE		_MMIO(0x46070)
6224 #define   ICL_CDCLK_PLL_RATIO_MASK	0xff
6227 #define DC_STATE_EN			_MMIO(0x45504)
6228 #define  DC_STATE_DISABLE		0
6233 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
6235 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
6236 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
6238 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
6239 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
6242 #define D_COMP_BDW			_MMIO(0x138144)
6245 #define _WM_LINETIME_A		0x45270
6246 #define _WM_LINETIME_B		0x45274
6248 #define  HSW_LINETIME_MASK	REG_GENMASK(8, 0)
6254 #define SFUSE_STRAP			_MMIO(0xc2014)
6262 #define  SFUSE_STRAP_DDID_DETECTED	(1 << 0)
6264 #define WM_MISC				_MMIO(0x45260)
6265 #define  WM_MISC_DATA_PARTITION_5_6	(1 << 0)
6267 #define WM_DBG				_MMIO(0x45280)
6268 #define  WM_DBG_DISALLOW_MULTIPLE_LP	(1 << 0)
6273 #define _PIPE_A_CSC_COEFF_RY_GY	0x49010
6274 #define _PIPE_A_CSC_COEFF_BY	0x49014
6275 #define _PIPE_A_CSC_COEFF_RU_GU	0x49018
6276 #define _PIPE_A_CSC_COEFF_BU	0x4901c
6277 #define _PIPE_A_CSC_COEFF_RV_GV	0x49020
6278 #define _PIPE_A_CSC_COEFF_BV	0x49024
6280 #define _PIPE_A_CSC_MODE	0x49028
6285 #define  CSC_MODE_YUV_TO_RGB		(1 << 0) /* ilk/snb */
6287 #define _PIPE_A_CSC_PREOFF_HI	0x49030
6288 #define _PIPE_A_CSC_PREOFF_ME	0x49034
6289 #define _PIPE_A_CSC_PREOFF_LO	0x49038
6290 #define _PIPE_A_CSC_POSTOFF_HI	0x49040
6291 #define _PIPE_A_CSC_POSTOFF_ME	0x49044
6292 #define _PIPE_A_CSC_POSTOFF_LO	0x49048
6294 #define _PIPE_B_CSC_COEFF_RY_GY	0x49110
6295 #define _PIPE_B_CSC_COEFF_BY	0x49114
6296 #define _PIPE_B_CSC_COEFF_RU_GU	0x49118
6297 #define _PIPE_B_CSC_COEFF_BU	0x4911c
6298 #define _PIPE_B_CSC_COEFF_RV_GV	0x49120
6299 #define _PIPE_B_CSC_COEFF_BV	0x49124
6300 #define _PIPE_B_CSC_MODE	0x49128
6301 #define _PIPE_B_CSC_PREOFF_HI	0x49130
6302 #define _PIPE_B_CSC_PREOFF_ME	0x49134
6303 #define _PIPE_B_CSC_PREOFF_LO	0x49138
6304 #define _PIPE_B_CSC_POSTOFF_HI	0x49140
6305 #define _PIPE_B_CSC_POSTOFF_ME	0x49144
6306 #define _PIPE_B_CSC_POSTOFF_LO	0x49148
6323 #define _PIPE_A_OUTPUT_CSC_COEFF_RY_GY	0x49050
6324 #define _PIPE_A_OUTPUT_CSC_COEFF_BY	0x49054
6325 #define _PIPE_A_OUTPUT_CSC_COEFF_RU_GU	0x49058
6326 #define _PIPE_A_OUTPUT_CSC_COEFF_BU	0x4905c
6327 #define _PIPE_A_OUTPUT_CSC_COEFF_RV_GV	0x49060
6328 #define _PIPE_A_OUTPUT_CSC_COEFF_BV	0x49064
6329 #define _PIPE_A_OUTPUT_CSC_PREOFF_HI	0x49068
6330 #define _PIPE_A_OUTPUT_CSC_PREOFF_ME	0x4906c
6331 #define _PIPE_A_OUTPUT_CSC_PREOFF_LO	0x49070
6332 #define _PIPE_A_OUTPUT_CSC_POSTOFF_HI	0x49074
6333 #define _PIPE_A_OUTPUT_CSC_POSTOFF_ME	0x49078
6334 #define _PIPE_A_OUTPUT_CSC_POSTOFF_LO	0x4907c
6336 #define _PIPE_B_OUTPUT_CSC_COEFF_RY_GY	0x49150
6337 #define _PIPE_B_OUTPUT_CSC_COEFF_BY	0x49154
6338 #define _PIPE_B_OUTPUT_CSC_COEFF_RU_GU	0x49158
6339 #define _PIPE_B_OUTPUT_CSC_COEFF_BU	0x4915c
6340 #define _PIPE_B_OUTPUT_CSC_COEFF_RV_GV	0x49160
6341 #define _PIPE_B_OUTPUT_CSC_COEFF_BV	0x49164
6342 #define _PIPE_B_OUTPUT_CSC_PREOFF_HI	0x49168
6343 #define _PIPE_B_OUTPUT_CSC_PREOFF_ME	0x4916c
6344 #define _PIPE_B_OUTPUT_CSC_PREOFF_LO	0x49170
6345 #define _PIPE_B_OUTPUT_CSC_POSTOFF_HI	0x49174
6346 #define _PIPE_B_OUTPUT_CSC_POSTOFF_ME	0x49178
6347 #define _PIPE_B_OUTPUT_CSC_POSTOFF_LO	0x4917c
6387 #define _PAL_PREC_INDEX_A	0x4A400
6388 #define _PAL_PREC_INDEX_B	0x4AC00
6389 #define _PAL_PREC_INDEX_C	0x4B400
6392 #define   PAL_PREC_INDEX_VALUE_MASK	REG_GENMASK(9, 0)
6394 #define _PAL_PREC_DATA_A	0x4A404
6395 #define _PAL_PREC_DATA_B	0x4AC04
6396 #define _PAL_PREC_DATA_C	0x4B404
6398 #define _PAL_PREC_GC_MAX_A	0x4A410
6399 #define _PAL_PREC_GC_MAX_B	0x4AC10
6400 #define _PAL_PREC_GC_MAX_C	0x4B410
6401 #define _PAL_PREC_EXT_GC_MAX_A	0x4A420
6402 #define _PAL_PREC_EXT_GC_MAX_B	0x4AC20
6403 #define _PAL_PREC_EXT_GC_MAX_C	0x4B420
6404 #define _PAL_PREC_EXT2_GC_MAX_A	0x4A430
6405 #define _PAL_PREC_EXT2_GC_MAX_B	0x4AC30
6406 #define _PAL_PREC_EXT2_GC_MAX_C	0x4B430
6414 #define _PRE_CSC_GAMC_INDEX_A	0x4A484
6415 #define _PRE_CSC_GAMC_INDEX_B	0x4AC84
6416 #define _PRE_CSC_GAMC_INDEX_C	0x4B484
6418 #define   PRE_CSC_GAMC_INDEX_VALUE_MASK	REG_GENMASK(7, 0)
6420 #define _PRE_CSC_GAMC_DATA_A	0x4A488
6421 #define _PRE_CSC_GAMC_DATA_B	0x4AC88
6422 #define _PRE_CSC_GAMC_DATA_C	0x4B488
6428 #define _PAL_PREC_MULTI_SEG_INDEX_A	0x4A408
6429 #define _PAL_PREC_MULTI_SEG_INDEX_B	0x4AC08
6431 #define   PAL_PREC_MULTI_SEG_INDEX_VALUE_MASK	REG_GENMASK(4, 0)
6434 #define _PAL_PREC_MULTI_SEG_DATA_A	0x4A40C
6435 #define _PAL_PREC_MULTI_SEG_DATA_B	0x4AC0C
6448 #define _PLANE_CSC_RY_GY_1_A	0x70210
6449 #define _PLANE_CSC_RY_GY_2_A	0x70310
6451 #define _PLANE_CSC_RY_GY_1_B	0x71210
6452 #define _PLANE_CSC_RY_GY_2_B	0x71310
6462 #define _PLANE_CSC_PREOFF_HI_1_A		0x70228
6463 #define _PLANE_CSC_PREOFF_HI_2_A		0x70328
6465 #define _PLANE_CSC_PREOFF_HI_1_B		0x71228
6466 #define _PLANE_CSC_PREOFF_HI_2_B		0x71328
6476 #define _PLANE_CSC_POSTOFF_HI_1_A		0x70234
6477 #define _PLANE_CSC_POSTOFF_HI_2_A		0x70334
6479 #define _PLANE_CSC_POSTOFF_HI_1_B		0x71234
6480 #define _PLANE_CSC_POSTOFF_HI_2_B		0x71334
6490 #define _PIPE_A_WGC_C01_C00	0x600B0 /* s2.10 */
6491 #define _PIPE_A_WGC_C02		0x600B4 /* s2.10 */
6492 #define _PIPE_A_WGC_C11_C10	0x600B8 /* s2.10 */
6493 #define _PIPE_A_WGC_C12		0x600BC /* s2.10 */
6494 #define _PIPE_A_WGC_C21_C20	0x600C0 /* s2.10 */
6495 #define _PIPE_A_WGC_C22		0x600C4 /* s2.10 */
6505 #define _CGM_PIPE_A_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x67900)
6506 #define _CGM_PIPE_A_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x67904)
6507 #define _CGM_PIPE_A_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x67908)
6508 #define _CGM_PIPE_A_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6790C)
6509 #define _CGM_PIPE_A_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x67910)
6510 #define _CGM_PIPE_A_DEGAMMA	(VLV_DISPLAY_BASE + 0x66000)
6513 #define   CGM_PIPE_DEGAMMA_BLUE_LDW_MASK	REG_GENMASK(13, 0)
6515 #define   CGM_PIPE_DEGAMMA_RED_UDW_MASK		REG_GENMASK(13, 0)
6516 #define _CGM_PIPE_A_GAMMA	(VLV_DISPLAY_BASE + 0x67000)
6519 #define   CGM_PIPE_GAMMA_BLUE_LDW_MASK		REG_GENMASK(9, 0)
6521 #define   CGM_PIPE_GAMMA_RED_UDW_MASK		REG_GENMASK(9, 0)
6522 #define _CGM_PIPE_A_MODE	(VLV_DISPLAY_BASE + 0x67A00)
6525 #define   CGM_PIPE_MODE_DEGAMMA	(1 << 0)
6527 #define _CGM_PIPE_B_CSC_COEFF01	(VLV_DISPLAY_BASE + 0x69900)
6528 #define _CGM_PIPE_B_CSC_COEFF23	(VLV_DISPLAY_BASE + 0x69904)
6529 #define _CGM_PIPE_B_CSC_COEFF45	(VLV_DISPLAY_BASE + 0x69908)
6530 #define _CGM_PIPE_B_CSC_COEFF67	(VLV_DISPLAY_BASE + 0x6990C)
6531 #define _CGM_PIPE_B_CSC_COEFF8	(VLV_DISPLAY_BASE + 0x69910)
6532 #define _CGM_PIPE_B_DEGAMMA	(VLV_DISPLAY_BASE + 0x68000)
6533 #define _CGM_PIPE_B_GAMMA	(VLV_DISPLAY_BASE + 0x69000)
6534 #define _CGM_PIPE_B_MODE	(VLV_DISPLAY_BASE + 0x69A00)
6546 #define GEN4_TIMESTAMP		_MMIO(0x2358)
6547 #define ILK_TIMESTAMP_HI	_MMIO(0x70070)
6548 #define IVB_TIMESTAMP_CTR	_MMIO(0x44070)
6550 #define GEN9_TIMESTAMP_OVERRIDE				_MMIO(0x44074)
6551 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT	0
6552 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK	0x3ff
6554 #define  GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	(0xf << 12)
6557 #define _PIPE_FRMTMSTMP_A		0x70048
6558 #define _PIPE_FRMTMSTMP_B		0x71048
6563 #define _PIPE_FLIPTMSTMP_A		0x7004C
6564 #define _PIPE_FLIPTMSTMP_B		0x7104C
6569 #define _PIPE_FLIPDONETMSTMP_A		0x70054
6570 #define _PIPE_FLIPDONETMSTMP_B		0x71054
6574 #define _VLV_PIPE_MSA_MISC_A			0x70048
6578 #define   VLV_MSA_MISC1_SW_S3D_MASK			REG_GENMASK(2, 0) /* MSA MISC1 3:1 */
6580 #define GGC				_MMIO(0x108040)
6584 #define GEN12_GSMBASE			_MMIO(0x108100)
6585 #define GEN12_DSMBASE			_MMIO(0x1080C0)
6588 #define XEHP_CLOCK_GATE_DIS		_MMIO(0x101014)
6593 #define _ICL_PHY_MISC_A		0x64C00
6594 #define _ICL_PHY_MISC_B		0x64C04
6595 #define _DG2_PHY_MISC_TC1	0x64C14 /* TC1="PHY E" but offset as if "PHY F" */
6603 #define PORT_TX_DFLEXDPSP(fia)			_MMIO_FIA((fia), 0x008A0)
6608 #define   DP_LANE_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 8))
6611 #define PORT_TX_DFLEXDPPMS(fia)			_MMIO_FIA((fia), 0x00890)
6614 #define PORT_TX_DFLEXDPCSSS(fia)		_MMIO_FIA((fia), 0x00894)
6617 #define PORT_TX_DFLEXPA1(fia)			_MMIO_FIA((fia), 0x00880)
6619 #define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
6622 #define _TCSS_DDI_STATUS_1			0x161500
6623 #define _TCSS_DDI_STATUS_2			0x161504
6629 #define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
6631 #define PRIMARY_SPI_TRIGGER			_MMIO(0x102040)
6632 #define PRIMARY_SPI_ADDRESS			_MMIO(0x102080)
6633 #define PRIMARY_SPI_REGIONID			_MMIO(0x102084)
6634 #define SPI_STATIC_REGIONS			_MMIO(0x102090)
6635 #define   OPTIONROM_SPI_REGIONID_MASK		REG_GENMASK(7, 0)
6636 #define OROM_OFFSET				_MMIO(0x1020c0)
6639 #define CLKREQ_POLICY			_MMIO(0x101038)
6642 #define CLKGATE_DIS_MISC			_MMIO(0x46534)
6645 #define _MTL_CLKGATE_DIS_TRANS_A			0x604E8
6646 #define _MTL_CLKGATE_DIS_TRANS_B			0x614E8
6650 #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
6653 #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
6655 #define MTL_MEM_SS_INFO_QGV_POINT_OFFSET	0x45710
6659 #define   MTL_DCLK_MASK			REG_GENMASK(15, 0)
6663 #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
6665 #define MTL_MEDIA_GSI_BASE		0x380000