Lines Matching refs:raw_reg_write
438 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); in ilk_irq_handler()
447 raw_reg_write(regs, SDEIER, 0); in ilk_irq_handler()
454 raw_reg_write(regs, GTIIR, gt_iir); in ilk_irq_handler()
464 raw_reg_write(regs, DEIIR, de_iir); in ilk_irq_handler()
475 raw_reg_write(regs, GEN6_PMIIR, pm_iir); in ilk_irq_handler()
481 raw_reg_write(regs, DEIER, de_ier); in ilk_irq_handler()
483 raw_reg_write(regs, SDEIER, sde_ier); in ilk_irq_handler()
495 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); in gen8_master_intr_disable()
508 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in gen8_master_intr_enable()
545 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0); in gen11_master_intr_disable()
558 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); in gen11_master_intr_enable()
601 raw_reg_write(regs, DG1_MSTR_TILE_INTR, 0); in dg1_master_intr_disable()
608 raw_reg_write(regs, DG1_MSTR_TILE_INTR, val); in dg1_master_intr_disable()
615 raw_reg_write(regs, DG1_MSTR_TILE_INTR, DG1_MSTR_IRQ); in dg1_master_intr_enable()
638 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, master_ctl); in dg1_irq_handler()