Lines Matching refs:intel_uncore_posting_read

85 	intel_uncore_posting_read(uncore, imr);  in gen3_irq_reset()
91 	intel_uncore_posting_read(uncore, iir);  in gen3_irq_reset()
93 	intel_uncore_posting_read(uncore, iir);  in gen3_irq_reset()
124 	intel_uncore_posting_read(uncore, reg);  in gen3_assert_iir_is_zero()
126 	intel_uncore_posting_read(uncore, reg);  in gen3_assert_iir_is_zero()
154 	intel_uncore_posting_read(uncore, imr);  in gen3_irq_init()
198 	intel_uncore_posting_read(&dev_priv->uncore, GEN7_MISCCPCTL);  in ivb_parity_work()
218 		intel_uncore_posting_read(&dev_priv->uncore, reg);  in ivb_parity_work()
700 	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);  in valleyview_irq_reset()
761 	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);  in cherryview_irq_reset()
790 	intel_uncore_posting_read(&dev_priv->uncore, VLV_MASTER_IER);  in valleyview_irq_postinstall()
813 	intel_uncore_posting_read(&dev_priv->uncore, GEN11_GFX_MSTR_IRQ);  in gen11_irq_postinstall()
831 	intel_uncore_posting_read(uncore, DG1_MSTR_TILE_INTR);  in dg1_irq_postinstall()
844 	intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ);  in cherryview_irq_postinstall()