Lines Matching refs:engine_mmio_list

170 	u32 cnt = gvt->engine_mmio_list.mocs_mmio_offset_list_cnt;  in load_render_mocs()
171 	u32 *regs = gvt->engine_mmio_list.mocs_mmio_offset_list;  in load_render_mocs()
209 	int count = gvt->engine_mmio_list.ctx_mmio_count[ring_id];  in restore_context_mmio_for_inhibit()
223 	for (mmio = gvt->engine_mmio_list.mmio;  in restore_context_mmio_for_inhibit()
358 	u32 *regs = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list;  in handle_tlb_pending_event()
359 	u32 cnt = vgpu->gvt->engine_mmio_list.tlb_mmio_offset_list_cnt;  in handle_tlb_pending_event()
485 	for (mmio = engine->i915->gvt->engine_mmio_list.mmio;  in switch_mmio()
589 		gvt->engine_mmio_list.mmio = gen9_engine_mmio_list;  in intel_gvt_init_engine_mmio_context()
590 		gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;  in intel_gvt_init_engine_mmio_context()
591 		gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);  in intel_gvt_init_engine_mmio_context()
592 		gvt->engine_mmio_list.mocs_mmio_offset_list = gen9_mocs_mmio_offset_list;  in intel_gvt_init_engine_mmio_context()
593 		gvt->engine_mmio_list.mocs_mmio_offset_list_cnt = ARRAY_SIZE(gen9_mocs_mmio_offset_list);  in intel_gvt_init_engine_mmio_context()
595 		gvt->engine_mmio_list.mmio = gen8_engine_mmio_list;  in intel_gvt_init_engine_mmio_context()
596 		gvt->engine_mmio_list.tlb_mmio_offset_list = gen8_tlb_mmio_offset_list;  in intel_gvt_init_engine_mmio_context()
597 		gvt->engine_mmio_list.tlb_mmio_offset_list_cnt = ARRAY_SIZE(gen8_tlb_mmio_offset_list);  in intel_gvt_init_engine_mmio_context()
600 	for (mmio = gvt->engine_mmio_list.mmio;  in intel_gvt_init_engine_mmio_context()
603 			gvt->engine_mmio_list.ctx_mmio_count[mmio->id]++;  in intel_gvt_init_engine_mmio_context()