2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
45 #define iir_to_regbase(iir)    (iir - 0x8)
46 #define ier_to_regbase(ier)    (ier - 0xC)
48 #define get_event_virt_handler(irq, e)	(irq->events[e].v_handler)
49 #define get_irq_info(irq, e)		(irq->events[e].info)
93 	[PIPE_A_ODD_FIELD] = "Pipe A odd field",
94 	[PIPE_A_EVEN_FIELD] = "Pipe A even field",
101 	[PIPE_B_ODD_FIELD] = "Pipe B odd field",
102 	[PIPE_B_EVEN_FIELD] = "Pipe B even field",
132 	[ERR_AND_DBG] = "South Error and Debug Interrupts Combined",
153 	struct intel_gvt_irq *irq = &gvt->irq;  in regbase_to_irq_info()
156 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {  in regbase_to_irq_info()
157 		if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)  in regbase_to_irq_info()
158 			return irq->info[i];  in regbase_to_irq_info()
165  * intel_vgpu_reg_imr_handler - Generic IMR register emulation write handler
181 	struct intel_gvt *gvt = vgpu->gvt;  in intel_vgpu_reg_imr_handler()
182 	const struct intel_gvt_irq_ops *ops = gvt->irq.ops;  in intel_vgpu_reg_imr_handler()
185 	trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),  in intel_vgpu_reg_imr_handler()
190 	ops->check_pending_irq(vgpu);  in intel_vgpu_reg_imr_handler()
196  * intel_vgpu_reg_master_irq_handler - master IRQ write emulation handler
211 	struct intel_gvt *gvt = vgpu->gvt;  in intel_vgpu_reg_master_irq_handler()
212 	const struct intel_gvt_irq_ops *ops = gvt->irq.ops;  in intel_vgpu_reg_master_irq_handler()
216 	trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,  in intel_vgpu_reg_master_irq_handler()
229 	ops->check_pending_irq(vgpu);  in intel_vgpu_reg_master_irq_handler()
235  * intel_vgpu_reg_ier_handler - Generic IER write emulation handler
250 	struct intel_gvt *gvt = vgpu->gvt;  in intel_vgpu_reg_ier_handler()
251 	struct drm_i915_private *i915 = gvt->gt->i915;  in intel_vgpu_reg_ier_handler()
252 	const struct intel_gvt_irq_ops *ops = gvt->irq.ops;  in intel_vgpu_reg_ier_handler()
256 	trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),  in intel_vgpu_reg_ier_handler()
262 	if (drm_WARN_ON(&i915->drm, !info))  in intel_vgpu_reg_ier_handler()
263 		return -EINVAL;  in intel_vgpu_reg_ier_handler()
265 	if (info->has_upstream_irq)  in intel_vgpu_reg_ier_handler()
268 	ops->check_pending_irq(vgpu);  in intel_vgpu_reg_ier_handler()
274  * intel_vgpu_reg_iir_handler - Generic IIR write emulation handler
289 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_vgpu_reg_iir_handler()
290 	struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,  in intel_vgpu_reg_iir_handler()
294 	trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),  in intel_vgpu_reg_iir_handler()
297 	if (drm_WARN_ON(&i915->drm, !info))  in intel_vgpu_reg_iir_handler()
298 		return -EINVAL;  in intel_vgpu_reg_iir_handler()
302 	if (info->has_upstream_irq)  in intel_vgpu_reg_iir_handler()
321 	{ -1, -1, ~0 },
327 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in update_upstream_irq()
328 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;  in update_upstream_irq()
329 	struct intel_gvt_irq_map *map = irq->irq_map;  in update_upstream_irq()
335 			regbase_to_iir(i915_mmio_reg_offset(info->reg_base)))  in update_upstream_irq()
337 			regbase_to_ier(i915_mmio_reg_offset(info->reg_base)));  in update_upstream_irq()
339 	if (!info->has_upstream_irq)  in update_upstream_irq()
342 	for (map = irq->irq_map; map->up_irq_bit != -1; map++) {  in update_upstream_irq()
343 		if (info->group != map->down_irq_group)  in update_upstream_irq()
347 			up_irq_info = irq->info[map->up_irq_group];  in update_upstream_irq()
349 			drm_WARN_ON(&i915->drm, up_irq_info !=  in update_upstream_irq()
350 				    irq->info[map->up_irq_group]);  in update_upstream_irq()
352 		bit = map->up_irq_bit;  in update_upstream_irq()
354 		if (val & map->down_irq_bitmask)  in update_upstream_irq()
360 	if (drm_WARN_ON(&i915->drm, !up_irq_info))  in update_upstream_irq()
363 	if (up_irq_info->group == INTEL_GVT_IRQ_INFO_MASTER) {  in update_upstream_irq()
364 		u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base);  in update_upstream_irq()
370 			i915_mmio_reg_offset(up_irq_info->reg_base));  in update_upstream_irq()
372 			i915_mmio_reg_offset(up_irq_info->reg_base));  in update_upstream_irq()
377 	if (up_irq_info->has_upstream_irq)  in update_upstream_irq()
387 	for (map = irq->irq_map; map->up_irq_bit != -1; map++) {  in init_irq_map()
388 		up_info = irq->info[map->up_irq_group];  in init_irq_map()
389 		up_bit = map->up_irq_bit;  in init_irq_map()
390 		down_info = irq->info[map->down_irq_group];  in init_irq_map()
392 		set_bit(up_bit, up_info->downstream_irq_bitmap);  in init_irq_map()
393 		down_info->has_upstream_irq = true;  in init_irq_map()
395 		gvt_dbg_irq("[up] grp %d bit %d -> [down] grp %d bitmask %x\n",  in init_irq_map()
396 			up_info->group, up_bit,  in init_irq_map()
397 			down_info->group, map->down_irq_bitmask);  in init_irq_map()
410 	unsigned long offset = vgpu->gvt->device_info.msi_cap_offset;  in inject_virtual_interrupt()
425 	trace_inject_msi(vgpu->id, addr, data);  in inject_virtual_interrupt()
436 	if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))  in inject_virtual_interrupt()
438 	if (vgpu->msi_trigger)  in inject_virtual_interrupt()
439 		eventfd_signal(vgpu->msi_trigger, 1);  in inject_virtual_interrupt()
453 	reg_base = i915_mmio_reg_offset(info->reg_base);  in propagate_event()
454 	bit = irq->events[event].bit;  in propagate_event()
458 		trace_propagate_event(vgpu->id, irq_name[event], bit);  in propagate_event()
468 	if (!vgpu->irq.irq_warn_once[event]) {  in handle_default_event_virt()
470 			vgpu->id, event, irq_name[event]);  in handle_default_event_virt()
471 		vgpu->irq.irq_warn_once[event] = true;  in handle_default_event_virt()
481 	.name = #regname"-IRQ", \
483 	.bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] = \
500 	.name = "PCH-IRQ",
502 	.bit_to_event = {[0 ... INTEL_GVT_IRQ_BITWIDTH-1] =
508 	struct intel_gvt_irq *irq = &vgpu->gvt->irq;  in gen8_check_pending_irq()
515 	for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {  in gen8_check_pending_irq()
516 		struct intel_gvt_irq_info *info = irq->info[i];  in gen8_check_pending_irq()
519 		if (!info->has_upstream_irq)  in gen8_check_pending_irq()
522 		reg_base = i915_mmio_reg_offset(info->reg_base);  in gen8_check_pending_irq()
540 		s->events[e].bit = b;		\  in gen8_init_irq()
541 		s->events[e].info = s->info[i];	\  in gen8_init_irq()
542 		s->info[i]->bit_to_event[b] = e;\  in gen8_init_irq()
547 		s->info[g] = i; \  in gen8_init_irq()
548 		(i)->group = g; \  in gen8_init_irq()
549 		set_bit(g, s->irq_info_bitmap); \  in gen8_init_irq()
581 	if (HAS_ENGINE(gvt->gt, VCS1)) {  in gen8_init_irq()
613 	if (IS_BROADWELL(gvt->gt->i915)) {  in gen8_init_irq()
626 	} else if (GRAPHICS_VER(gvt->gt->i915) >= 9) {  in gen8_init_irq()
651  * intel_vgpu_trigger_virtual_event - Trigger a virtual event for a vGPU
663 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;  in intel_vgpu_trigger_virtual_event()
664 	struct intel_gvt *gvt = vgpu->gvt;  in intel_vgpu_trigger_virtual_event()
665 	struct intel_gvt_irq *irq = &gvt->irq;  in intel_vgpu_trigger_virtual_event()
667 	const struct intel_gvt_irq_ops *ops = gvt->irq.ops;  in intel_vgpu_trigger_virtual_event()
670 	drm_WARN_ON(&i915->drm, !handler);  in intel_vgpu_trigger_virtual_event()
674 	ops->check_pending_irq(vgpu);  in intel_vgpu_trigger_virtual_event()
683 		irq->events[i].info = NULL;  in init_events()
684 		irq->events[i].v_handler = handle_default_event_virt;  in init_events()
689  * intel_gvt_init_irq - initialize GVT-g IRQ emulation subsystem
692  * This function is called at driver loading stage, to initialize the GVT-g IRQ
700 	struct intel_gvt_irq *irq = &gvt->irq;  in intel_gvt_init_irq()
704 	irq->ops = &gen8_irq_ops;  in intel_gvt_init_irq()
705 	irq->irq_map = gen8_irq_map;  in intel_gvt_init_irq()
711 	irq->ops->init_irq(irq);  in intel_gvt_init_irq()