Lines Matching +full:0 +full:x4094
57 #define PCH_PP_STATUS _MMIO(0xc7200)
58 #define PCH_PP_CONTROL _MMIO(0xc7204)
59 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
60 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
61 #define PCH_PP_DIVISOR _MMIO(0xc7210)
78 return 0; in intel_gvt_get_device_type()
119 return 0; in setup_mmio_info()
141 return 0; in setup_mmio_info()
158 offset &= ~GENMASK(11, 0); in intel_gvt_render_mmio_to_engine()
167 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
170 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
209 memset(p_data, 0, bytes); in sanitize_fence_mmio_access()
212 return 0; in sanitize_fence_mmio_access()
237 return 0; in gamw_echo_dev_rw_ia_write()
250 return 0; in fence_mmio_read()
269 return 0; in fence_mmio_write()
274 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
299 gvt_vgpu_err("invalid forcewake offset 0x%x\n", offset); in mul_force_wake_write()
307 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0)); in mul_force_wake_write()
308 return 0; in mul_force_wake_write()
314 intel_engine_mask_t engine_mask = 0; in gdrst_mmio_write()
355 vgpu_vreg(vgpu, offset) = 0; in gdrst_mmio_write()
357 return 0; in gdrst_mmio_write()
387 return 0; in pch_pp_control_mmio_write()
399 return 0; in transconf_mmio_write()
417 return 0; in lcpll_ctl_mmio_write()
424 case 0xe651c: in dpy_reg_mmio_read()
425 case 0xe661c: in dpy_reg_mmio_read()
426 case 0xe671c: in dpy_reg_mmio_read()
427 case 0xe681c: in dpy_reg_mmio_read()
430 case 0xe6c04: in dpy_reg_mmio_read()
431 vgpu_vreg(vgpu, offset) = 0x3; in dpy_reg_mmio_read()
433 case 0xe6e1c: in dpy_reg_mmio_read()
434 vgpu_vreg(vgpu, offset) = 0x2f << 16; in dpy_reg_mmio_read()
441 return 0; in dpy_reg_mmio_read()
462 u32 dp_br = 0; in bdw_vgpu_get_dp_bitrate()
488 gvt_dbg_dpy("vgpu-%d PORT_%c can't get freq from SPLL 0x%08x\n", in bdw_vgpu_get_dp_bitrate()
513 gvt_dbg_dpy("vgpu-%d PORT_%c WRPLL can't get refclk 0x%08x\n", in bdw_vgpu_get_dp_bitrate()
526 gvt_dbg_dpy("vgpu-%d PORT_%c has invalid clock select 0x%08x\n", in bdw_vgpu_get_dp_bitrate()
537 u32 dp_br = 0; in bxt_vgpu_get_dp_bitrate()
541 struct dpll clock = {0}; in bxt_vgpu_get_dp_bitrate()
565 gvt_dbg_dpy("vgpu-%d PORT_%c PLL_ENABLE 0x%08x isn't enabled or locked\n", in bxt_vgpu_get_dp_bitrate()
572 vgpu_vreg_t(vgpu, BXT_PORT_PLL(phy, ch, 0))) << 22; in bxt_vgpu_get_dp_bitrate()
585 if (clock.n == 0 || clock.p == 0) { in bxt_vgpu_get_dp_bitrate()
601 u32 dp_br = 0; in skl_vgpu_get_dp_bitrate()
639 dp_br = 0; in skl_vgpu_get_dp_bitrate()
678 u64 pixel_clk = 0; in vgpu_update_refresh_rate()
679 u32 new_rate = 0; in vgpu_update_refresh_rate()
687 …new_rate = DIV64_U64_ROUND_CLOSEST(mul_u64_u32_shr(pixel_clk, MSEC_PER_SEC, 0), mul_u32_u32(htotal… in vgpu_update_refresh_rate()
713 return 0; in pipeconf_mmio_write()
718 _MMIO(0xd80),
719 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
720 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
721 CL_PRIMITIVES_COUNT, //_MMIO(0x2340)
722 PS_INVOCATION_COUNT, //_MMIO(0x2348)
723 PS_DEPTH_COUNT, //_MMIO(0x2350)
724 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
725 _MMIO(0x2690),
726 _MMIO(0x2694),
727 _MMIO(0x2698),
728 _MMIO(0x2754),
729 _MMIO(0x28a0),
730 _MMIO(0x4de0),
731 _MMIO(0x4de4),
732 _MMIO(0x4dfc),
733 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
734 _MMIO(0x7014),
735 HDC_CHICKEN0,//_MMIO(0x7300)
736 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
737 _MMIO(0x7700),
738 _MMIO(0x7704),
739 _MMIO(0x7708),
740 _MMIO(0x770c),
741 _MMIO(0x83a8),
742 _MMIO(0xb110),
743 _MMIO(0xb118),
744 _MMIO(0xe100),
745 _MMIO(0xe18c),
746 _MMIO(0xe48c),
747 _MMIO(0xe5f4),
748 _MMIO(0x64844),
754 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list); in in_whitelist()
790 return 0; in force_nonpriv_write()
806 return 0; in ddi_buf_ctl_mmio_write()
813 return 0; in fdi_rx_iir_mmio_write()
816 #define FDI_LINK_TRAIN_PATTERN1 0
832 return 0; in fdi_auto_training_started()
865 return 0; in check_fdi_rx_train_status()
873 return 0; in check_fdi_rx_train_status()
876 #define INVALID_INDEX (~0U)
892 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
895 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
898 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
923 if (ret < 0) in update_fdi_rx_iir_status()
929 if (ret < 0) in update_fdi_rx_iir_status()
938 return 0; in update_fdi_rx_iir_status()
942 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
955 if (data == 0x2) { in dp_tp_ctl_mmio_write()
959 return 0; in dp_tp_ctl_mmio_write()
974 return 0; in dp_tp_status_mmio_write()
987 return 0; in pch_adpa_mmio_write()
1002 return 0; in south_chicken2_mmio_write()
1006 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
1025 return 0; in pri_surf_mmio_write()
1029 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
1045 return 0; in spr_surf_mmio_write()
1070 return 0; in reg50080_mmio_write()
1096 return 0; in trigger_aux_channel_interrupt()
1113 value &= ~(0xf << 20); in dp_aux_ch_ctl_trans_done()
1119 return 0; in dp_aux_ch_ctl_trans_done()
1152 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
1154 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
1156 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
1173 return 0; in dp_aux_ch_ctl_mmio_write()
1182 return 0; in dp_aux_ch_ctl_mmio_write()
1186 return 0; in dp_aux_ch_ctl_mmio_write()
1191 vgpu_vreg(vgpu, offset) = 0; in dp_aux_ch_ctl_mmio_write()
1192 return 0; in dp_aux_ch_ctl_mmio_write()
1200 addr = (msg >> 8) & 0xffff; in dp_aux_ch_ctl_mmio_write()
1201 ctrl = (msg >> 24) & 0xff; in dp_aux_ch_ctl_mmio_write()
1202 len = msg & 0xff; in dp_aux_ch_ctl_mmio_write()
1221 return 0; in dp_aux_ch_ctl_mmio_write()
1235 for (t = 0; t < 4; t++) { in dp_aux_ch_ctl_mmio_write()
1238 buf[t * 4] = (r >> 24) & 0xff; in dp_aux_ch_ctl_mmio_write()
1239 buf[t * 4 + 1] = (r >> 16) & 0xff; in dp_aux_ch_ctl_mmio_write()
1240 buf[t * 4 + 2] = (r >> 8) & 0xff; in dp_aux_ch_ctl_mmio_write()
1241 buf[t * 4 + 3] = r & 0xff; in dp_aux_ch_ctl_mmio_write()
1246 for (t = 0; t <= len; t++) { in dp_aux_ch_ctl_mmio_write()
1258 vgpu_vreg(vgpu, offset + 4) = 0; in dp_aux_ch_ctl_mmio_write()
1261 return 0; in dp_aux_ch_ctl_mmio_write()
1265 int idx, i, ret = 0; in dp_aux_ch_ctl_mmio_write()
1277 vgpu_vreg(vgpu, offset + 4) = 0; in dp_aux_ch_ctl_mmio_write()
1278 vgpu_vreg(vgpu, offset + 8) = 0; in dp_aux_ch_ctl_mmio_write()
1279 vgpu_vreg(vgpu, offset + 12) = 0; in dp_aux_ch_ctl_mmio_write()
1280 vgpu_vreg(vgpu, offset + 16) = 0; in dp_aux_ch_ctl_mmio_write()
1281 vgpu_vreg(vgpu, offset + 20) = 0; in dp_aux_ch_ctl_mmio_write()
1285 return 0; in dp_aux_ch_ctl_mmio_write()
1290 vgpu_vreg(vgpu, offset + 4 * idx) = 0; in dp_aux_ch_ctl_mmio_write()
1314 ret = 0; in dp_aux_ch_ctl_mmio_write()
1320 return 0; in dp_aux_ch_ctl_mmio_write()
1328 return 0; in dp_aux_ch_ctl_mmio_write()
1336 return 0; in mbctl_write()
1349 return 0; in vga_control_mmio_write()
1359 for (i = 0; i < num; ++i) in read_virtual_sbi_register()
1364 return 0; in read_virtual_sbi_register()
1376 for (i = 0; i < num; ++i) { in write_virtual_sbi_register()
1404 return 0; in sbi_data_mmio_read()
1431 return 0; in sbi_ctl_mmio_write()
1455 case 0x78010: /* vgt_caps */ in pvinfo_mmio_read()
1456 case 0x7881c: in pvinfo_mmio_read()
1466 return 0; in pvinfo_mmio_read()
1475 pdps = (u64 *)&vgpu_vreg64_t(vgpu, vgtif_reg(pdp[0])); in handle_g2v_notification()
1494 return 0; in handle_g2v_notification()
1505 env[0] = display_ready_str; in send_display_ready_uevent()
1521 send_display_ready_uevent(vgpu, data ? 1 : 0); in pvinfo_mmio_write()
1529 case _vgtif_reg(pdp[0].lo): in pvinfo_mmio_write()
1530 case _vgtif_reg(pdp[0].hi): in pvinfo_mmio_write()
1540 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): in pvinfo_mmio_write()
1554 return 0; in pvinfo_mmio_write()
1569 return 0; in pf_write()
1587 return 0; in power_well_ctl_mmio_write()
1600 return 0; in gen9_dbuf_ctl_mmio_write()
1610 return 0; in fpga_dbg_mmio_write()
1626 return 0; in dma_ctrl_write()
1629 return 0; in dma_ctrl_write()
1638 if ((trtte & 1) && (trtte & (1 << 1)) == 0) { in gen9_trtte_write()
1646 return 0; in gen9_trtte_write()
1653 return 0; in gen9_trtt_chicken_write()
1659 u32 v = 0; in dpll_status_read()
1661 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31)) in dpll_status_read()
1662 v |= (1 << 0); in dpll_status_read()
1664 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31)) in dpll_status_read()
1667 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31)) in dpll_status_read()
1670 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31)) in dpll_status_read()
1682 u32 cmd = value & 0xff; in mailbox_write()
1697 *data0 = 0x1e1a1100; in mailbox_write()
1699 *data0 = 0x61514b3d; in mailbox_write()
1707 *data0 = 0x16080707; in mailbox_write()
1709 *data0 = 0x16161616; in mailbox_write()
1720 *data0 |= 0x1; in mailbox_write()
1743 if (value != 0 && in hws_pga_write()
1745 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n", in hws_pga_write()
1756 gvt_vgpu_err("access unknown hardware status page register:0x%x\n", in hws_pga_write()
1761 gvt_dbg_mmio("VM(%d) write: 0x%x to HWSP: 0x%x\n", in hws_pga_write()
1793 return 0; in skl_lcpll_write()
1806 return 0; in bxt_de_pll_enable_write()
1819 return 0; in bxt_port_pll_enable_write()
1826 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0; in bxt_phy_ctl_family_write()
1840 return 0; in bxt_phy_ctl_family_write()
1861 vgpu_vreg(vgpu, offset - 0x600) = v; in bxt_pcs_dw12_grp_write()
1862 vgpu_vreg(vgpu, offset - 0x800) = v; in bxt_pcs_dw12_grp_write()
1864 vgpu_vreg(vgpu, offset - 0x400) = v; in bxt_pcs_dw12_grp_write()
1865 vgpu_vreg(vgpu, offset - 0x600) = v; in bxt_pcs_dw12_grp_write()
1870 return 0; in bxt_pcs_dw12_grp_write()
1878 if (v & BIT(0)) { in bxt_gt_disp_pwron_write()
1895 return 0; in bxt_gt_disp_pwron_write()
1901 vgpu_vreg(vgpu, offset) = 0; in edp_psr_imr_iir_write()
1902 return 0; in edp_psr_imr_iir_write()
1912 * PML4 PTE: PAT(0) PCD(1) PWT(1).
1919 GEN8_PPAT(0, CHV_PPAT_SNOOP) | in bxt_ppat_low_write()
1920 GEN8_PPAT(1, 0) | in bxt_ppat_low_write()
1921 GEN8_PPAT(2, 0) | in bxt_ppat_low_write()
1930 return 0; in bxt_ppat_low_write()
1940 return 0; in guc_status_read()
1977 int ret = 0; in elsp_mmio_write()
2008 execlist->elsp_dwords.index &= 0x3; in elsp_mmio_write()
2029 return 0; in ring_mode_mmio_write()
2036 return 0; in ring_mode_mmio_write()
2047 return 0; in ring_mode_mmio_write()
2058 return 0; in ring_mode_mmio_write()
2068 return 0; in ring_mode_mmio_write()
2074 unsigned int id = 0; in gvt_reg_tlb_control_handler()
2077 vgpu_vreg(vgpu, offset) = 0; in gvt_reg_tlb_control_handler()
2080 case 0x4260: in gvt_reg_tlb_control_handler()
2083 case 0x4264: in gvt_reg_tlb_control_handler()
2086 case 0x4268: in gvt_reg_tlb_control_handler()
2089 case 0x426c: in gvt_reg_tlb_control_handler()
2092 case 0x4270: in gvt_reg_tlb_control_handler()
2100 return 0; in gvt_reg_tlb_control_handler()
2117 return 0; in ring_reset_ctl_write()
2126 (*(u32 *)p_data) &= ~_MASKED_BIT_ENABLE(0x18); in csfe_chicken1_mmio_write()
2129 if (IS_MASKED_BITS_ENABLED(data, 0x10) || in csfe_chicken1_mmio_write()
2130 IS_MASKED_BITS_ENABLED(data, 0x8)) in csfe_chicken1_mmio_write()
2133 return 0; in csfe_chicken1_mmio_write()
2141 } while (0)
2144 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
2147 MMIO_F(reg, 4, f, 0, 0, d, r, w)
2150 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
2153 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
2156 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
2165 } while (0)
2168 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
2171 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
2174 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
2177 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
2184 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, in init_generic_mmio_info()
2187 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler); in init_generic_mmio_info()
2188 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler); in init_generic_mmio_info()
2189 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler); in init_generic_mmio_info()
2191 MMIO_RING_DFH(RING_HWSTAM, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
2201 #define RING_REG(base) _MMIO((base) + 0x28) in init_generic_mmio_info()
2205 #define RING_REG(base) _MMIO((base) + 0x134) in init_generic_mmio_info()
2209 #define RING_REG(base) _MMIO((base) + 0x6c) in init_generic_mmio_info()
2210 MMIO_RING_DFH(RING_REG, D_ALL, 0, mmio_read_from_hw, NULL); in init_generic_mmio_info()
2214 MMIO_GM_RDR(_MMIO(0x2148), D_ALL, NULL, NULL); in init_generic_mmio_info()
2216 MMIO_GM_RDR(_MMIO(0x12198), D_ALL, NULL, NULL); in init_generic_mmio_info()
2218 MMIO_RING_DFH(RING_TAIL, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
2219 MMIO_RING_DFH(RING_HEAD, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
2220 MMIO_RING_DFH(RING_CTL, D_ALL, 0, NULL, NULL); in init_generic_mmio_info()
2221 MMIO_RING_DFH(RING_ACTHD, D_ALL, 0, mmio_read_from_hw, NULL); in init_generic_mmio_info()
2225 #define RING_REG(base) _MMIO((base) + 0x29c) in init_generic_mmio_info()
2245 MMIO_DFH(_MMIO(0x2124), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2247 MMIO_DFH(_MMIO(0x20dc), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2249 MMIO_DFH(_MMIO(0x2088), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2252 MMIO_DFH(_MMIO(0x2470), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2258 MMIO_DFH(_MMIO(0x9030), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2259 MMIO_DFH(_MMIO(0x20a0), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2260 MMIO_DFH(_MMIO(0x2420), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2261 MMIO_DFH(_MMIO(0x2430), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2262 MMIO_DFH(_MMIO(0x2434), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2263 MMIO_DFH(_MMIO(0x2438), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2264 MMIO_DFH(_MMIO(0x243c), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2265 MMIO_DFH(_MMIO(0x7018), D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2293 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read, in init_generic_mmio_info()
2295 MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2297 MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, in init_generic_mmio_info()
2299 MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, in init_generic_mmio_info()
2301 MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, in init_generic_mmio_info()
2319 MMIO_DH(_MMIO(0xe651c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2320 MMIO_DH(_MMIO(0xe661c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2321 MMIO_DH(_MMIO(0xe671c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2322 MMIO_DH(_MMIO(0xe681c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2323 MMIO_DH(_MMIO(0xe6c04), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2324 MMIO_DH(_MMIO(0xe6e1c), D_ALL, dpy_reg_mmio_read, NULL); in init_generic_mmio_info()
2326 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0, in init_generic_mmio_info()
2339 MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, in init_generic_mmio_info()
2380 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write); in init_generic_mmio_info()
2390 MMIO_DFH(_MMIO(0x215c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2391 MMIO_DFH(_MMIO(0x2178), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2392 MMIO_DFH(_MMIO(0x217c), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2393 MMIO_DFH(_MMIO(0x12178), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2394 MMIO_DFH(_MMIO(0x1217c), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2396 MMIO_F(_MMIO(0x2290), 8, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); in init_generic_mmio_info()
2397 MMIO_F(_MMIO(0x5200), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2398 MMIO_F(_MMIO(0x5240), 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2399 MMIO_F(_MMIO(0x5280), 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2401 MMIO_DFH(_MMIO(0x1c17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2402 MMIO_DFH(_MMIO(0x1c178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2405 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2406 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2407 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2408 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2409 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2410 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2411 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2412 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2413 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2414 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2415 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL); in init_generic_mmio_info()
2416 MMIO_DH(_MMIO(0x4260), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2417 MMIO_DH(_MMIO(0x4264), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2418 MMIO_DH(_MMIO(0x4268), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2419 MMIO_DH(_MMIO(0x426c), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2420 MMIO_DH(_MMIO(0x4270), D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler); in init_generic_mmio_info()
2421 MMIO_DFH(_MMIO(0x4094), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2425 MMIO_DFH(_MMIO(0x2220), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2426 MMIO_DFH(_MMIO(0x12220), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2427 MMIO_DFH(_MMIO(0x22220), D_ALL, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2430 MMIO_DFH(_MMIO(0x22178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2431 MMIO_DFH(_MMIO(0x1a178), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2432 MMIO_DFH(_MMIO(0x1a17c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2433 MMIO_DFH(_MMIO(0x2217c), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_generic_mmio_info()
2439 return 0; in init_generic_mmio_info()
2446 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler); in init_bdw_mmio_info()
2447 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler); in init_bdw_mmio_info()
2448 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler); in init_bdw_mmio_info()
2498 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, 0, in init_bdw_mmio_info()
2501 #define RING_REG(base) _MMIO((base) + 0xd0) in init_bdw_mmio_info()
2502 MMIO_RING_F(RING_REG, 4, F_RO, 0, in init_bdw_mmio_info()
2507 #define RING_REG(base) _MMIO((base) + 0x230) in init_bdw_mmio_info()
2508 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write); in init_bdw_mmio_info()
2511 #define RING_REG(base) _MMIO((base) + 0x234) in init_bdw_mmio_info()
2512 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, in init_bdw_mmio_info()
2516 #define RING_REG(base) _MMIO((base) + 0x244) in init_bdw_mmio_info()
2520 #define RING_REG(base) _MMIO((base) + 0x370) in init_bdw_mmio_info()
2521 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL); in init_bdw_mmio_info()
2524 #define RING_REG(base) _MMIO((base) + 0x3a0) in init_bdw_mmio_info()
2530 #define RING_REG(base) _MMIO((base) + 0x270) in init_bdw_mmio_info()
2531 MMIO_RING_F(RING_REG, 32, F_CMD_ACCESS, 0, 0, D_BDW_PLUS, NULL, NULL); in init_bdw_mmio_info()
2544 MMIO_DFH(_MMIO(0xb1f0), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2545 MMIO_DFH(_MMIO(0xb1c0), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2547 MMIO_DFH(_MMIO(0xb100), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2548 MMIO_DFH(_MMIO(0xb10c), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2550 MMIO_F(_MMIO(0x24d0), 48, F_CMD_ACCESS | F_CMD_WRITE_PATCH, 0, 0, in init_bdw_mmio_info()
2553 MMIO_DFH(_MMIO(0x83a4), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2555 MMIO_DFH(_MMIO(0x8430), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2557 MMIO_DFH(_MMIO(0xe194), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2558 MMIO_DFH(_MMIO(0xe188), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2560 MMIO_DFH(_MMIO(0x2580), D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2562 MMIO_DFH(_MMIO(0x2248), D_BDW, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2564 MMIO_DFH(_MMIO(0xe220), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2565 MMIO_DFH(_MMIO(0xe230), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2566 MMIO_DFH(_MMIO(0xe240), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2567 MMIO_DFH(_MMIO(0xe260), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2568 MMIO_DFH(_MMIO(0xe270), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2569 MMIO_DFH(_MMIO(0xe280), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2570 MMIO_DFH(_MMIO(0xe2a0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2571 MMIO_DFH(_MMIO(0xe2b0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2572 MMIO_DFH(_MMIO(0xe2c0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2573 MMIO_DFH(_MMIO(0x21f0), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_bdw_mmio_info()
2574 return 0; in init_bdw_mmio_info()
2589 MMIO_F(DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, in init_skl_mmio_info()
2591 MMIO_F(DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, in init_skl_mmio_info()
2593 MMIO_F(DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_SKL_PLUS, NULL, in init_skl_mmio_info()
2598 MMIO_DH(DBUF_CTL_S(0), D_SKL_PLUS, NULL, gen9_dbuf_ctl_mmio_write); in init_skl_mmio_info()
2607 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
2609 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
2611 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
2614 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
2616 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
2618 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
2621 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
2623 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
2625 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL_PLUS, NULL, pf_write); in init_skl_mmio_info()
2628 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2633 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2638 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2647 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2651 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2655 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2663 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2668 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2673 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2710 MMIO_F(GEN9_GFX_MOCS(0), 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, in init_skl_mmio_info()
2712 MMIO_F(GEN7_L3CNTLREG2, 0x80, F_CMD_ACCESS, 0, 0, D_SKL_PLUS, in init_skl_mmio_info()
2721 MMIO_DFH(TRVATTL3PTRDW(0), D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); in init_skl_mmio_info()
2728 MMIO_DFH(_MMIO(0x4dfc), D_SKL_PLUS, F_PM_SAVE, in init_skl_mmio_info()
2734 #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) in init_skl_mmio_info()
2744 MMIO_DFH(_MMIO(0xe4cc), D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL); in init_skl_mmio_info()
2746 return 0; in init_skl_mmio_info()
2780 MMIO_DFH(_MMIO(0x20D8), D_BXT, F_CMD_ACCESS, NULL, NULL); in init_bxt_mmio_info()
2781 MMIO_F(GEN8_RING_CS_GPR(RENDER_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
2782 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
2783 MMIO_F(GEN8_RING_CS_GPR(GEN6_BSD_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
2784 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
2785 MMIO_F(GEN8_RING_CS_GPR(BLT_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
2786 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
2787 MMIO_F(GEN8_RING_CS_GPR(VEBOX_RING_BASE, 0), 0x40, F_CMD_ACCESS, in init_bxt_mmio_info()
2788 0, 0, D_BXT, NULL, NULL); in init_bxt_mmio_info()
2794 return 0; in init_bxt_mmio_info()
2804 for (i = 0; i < num; i++, block++) { in find_mmio_block()
2831 gvt->mmio.num_mmio_block = 0; in intel_gvt_clean_mmio_info()
2873 return 0; in handle_mmio()
2893 memset(block, 0, sizeof(*block)); in handle_mmio_block()
2900 return 0; in handle_mmio_block()
2906 if (size < 1024 || offset == i915_mmio_reg_offset(GEN9_GFX_MOCS(0))) in handle_mmio_cb()
2937 return 0; in init_mmio_block_handlers()
2999 return 0; in intel_gvt_setup_mmio_info()
3028 for (i = 0; i < gvt->mmio.num_mmio_block; i++, block++) { in intel_gvt_for_each_tracked_mmio()
3033 for (j = 0; j < block->size; j += 4) { in intel_gvt_for_each_tracked_mmio()
3039 return 0; in intel_gvt_for_each_tracked_mmio()
3056 return 0; in intel_vgpu_default_mmio_read()
3073 return 0; in intel_vgpu_default_mmio_write()
3097 return 0; in intel_vgpu_mask_mmio_write()
3165 u32 old_vreg = 0; in intel_vgpu_mmio_reg_rw()
3166 u64 data = 0; in intel_vgpu_mmio_reg_rw()
3176 return 0; in intel_vgpu_mmio_reg_rw()
3209 for (i = 0; i < vgpu_fence_sz(vgpu); i++) in intel_gvt_restore_fence()
3223 return 0; in mmio_pm_restore_handler()