Lines Matching refs:mmio
202 struct intel_vgpu_mmio mmio; member
298 void *mmio; member
337 struct intel_gvt_mmio mmio; member
359 struct engine_mmio *mmio; member
466 (*(u32 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
468 (*(u32 *)(vgpu->mmio.vreg + (offset)))
470 (*(u64 *)(vgpu->mmio.vreg + i915_mmio_reg_offset(reg)))
472 (*(u64 *)(vgpu->mmio.vreg + (offset)))
604 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED; in intel_gvt_mmio_set_accessed()
618 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS; in intel_gvt_mmio_is_cmd_accessible()
631 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS; in intel_gvt_mmio_set_cmd_accessible()
643 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN; in intel_gvt_mmio_is_unalign()
658 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK; in intel_gvt_mmio_has_mode_mask()
674 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX; in intel_gvt_mmio_is_sr_in_ctx()
688 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX; in intel_gvt_mmio_set_sr_in_ctx()
703 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH; in intel_gvt_mmio_set_cmd_write_patch()
718 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH; in intel_gvt_mmio_is_cmd_write_patch()