72 	u8 *cfg_base = vgpu_cfg_space(vgpu);  in vgpu_pci_cfg_mem_write()
98 		pwr = (pci_power_t __force)(*(u16*)(&vgpu_cfg_space(vgpu)[off])  in vgpu_pci_cfg_mem_write()
129 	memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);  in intel_vgpu_emulate_cfg_read()
148 	u8 old = vgpu_cfg_space(vgpu)[offset];  in emulate_pci_command_write()
170 	u32 *pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);  in emulate_pci_rom_bar_write()
188 		vgpu_cfg_space(vgpu)[PCI_COMMAND] & PCI_COMMAND_MEMORY;  in emulate_pci_bar_write()
328 	memcpy(vgpu_cfg_space(vgpu), gvt->firmware.cfg_space,  in intel_vgpu_init_cfg_space()
332 		vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] =  in intel_vgpu_init_cfg_space()
334 		vgpu_cfg_space(vgpu)[PCI_CLASS_PROG] =  in intel_vgpu_init_cfg_space()
339 	gmch_ctl = (u16 *)(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_GMCH_CONTROL);  in intel_vgpu_init_cfg_space()
345 	vgpu_cfg_space(vgpu)[PCI_COMMAND] &= ~(PCI_COMMAND_IO  in intel_vgpu_init_cfg_space()
351 	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_1, 0, 4);  in intel_vgpu_init_cfg_space()
352 	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_3, 0, 4);  in intel_vgpu_init_cfg_space()
353 	memset(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_4, 0, 8);  in intel_vgpu_init_cfg_space()
354 	memset(vgpu_cfg_space(vgpu) + INTEL_GVT_PCI_OPREGION, 0, 4);  in intel_vgpu_init_cfg_space()
361 	memset(vgpu_cfg_space(vgpu) + PCI_ROM_ADDRESS, 0, 4);  in intel_vgpu_init_cfg_space()
365 	if (vgpu_cfg_space(vgpu)[PCI_STATUS] & PCI_STATUS_CAP_LIST) {  in intel_vgpu_init_cfg_space()
366 		next = vgpu_cfg_space(vgpu)[PCI_CAPABILITY_LIST];  in intel_vgpu_init_cfg_space()
368 			if (vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_ID] == PCI_CAP_ID_PM) {  in intel_vgpu_init_cfg_space()
372 			next = vgpu_cfg_space(vgpu)[next + PCI_CAP_LIST_NEXT];  in intel_vgpu_init_cfg_space()
385 	u8 cmd = vgpu_cfg_space(vgpu)[PCI_COMMAND];  in intel_vgpu_reset_cfg_space()
386 	bool primary = vgpu_cfg_space(vgpu)[PCI_CLASS_DEVICE] !=  in intel_vgpu_reset_cfg_space()