Lines Matching refs:wal
97 static void wa_init_start(struct i915_wa_list *wal, struct intel_gt *gt, in wa_init_start() argument
100 wal->gt = gt; in wa_init_start()
101 wal->name = name; in wa_init_start()
102 wal->engine_name = engine_name; in wa_init_start()
107 static void wa_init_finish(struct i915_wa_list *wal) in wa_init_finish() argument
110 if (!IS_ALIGNED(wal->count, WA_LIST_CHUNK)) { in wa_init_finish()
111 struct i915_wa *list = kmemdup(wal->list, in wa_init_finish()
112 wal->count * sizeof(*list), in wa_init_finish()
116 kfree(wal->list); in wa_init_finish()
117 wal->list = list; in wa_init_finish()
121 if (!wal->count) in wa_init_finish()
124 drm_dbg(&wal->gt->i915->drm, "Initialized %u %s workarounds on %s\n", in wa_init_finish()
125 wal->wa_count, wal->name, wal->engine_name); in wa_init_finish()
129 wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal) in wal_get_fw_for_rmw() argument
135 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wal_get_fw_for_rmw()
144 static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa) in _wa_add() argument
147 struct drm_i915_private *i915 = wal->gt->i915; in _wa_add()
148 unsigned int start = 0, end = wal->count; in _wa_add()
154 if (IS_ALIGNED(wal->count, grow)) { /* Either uninitialized or full. */ in _wa_add()
157 list = kmalloc_array(ALIGN(wal->count + 1, grow), sizeof(*wa), in _wa_add()
164 if (wal->list) { in _wa_add()
165 memcpy(list, wal->list, sizeof(*wa) * wal->count); in _wa_add()
166 kfree(wal->list); in _wa_add()
169 wal->list = list; in _wa_add()
175 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { in _wa_add()
177 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { in _wa_add()
180 wa_ = &wal->list[mid]; in _wa_add()
191 wal->wa_count++; in _wa_add()
199 wal->wa_count++; in _wa_add()
200 wa_ = &wal->list[wal->count++]; in _wa_add()
203 while (wa_-- > wal->list) { in _wa_add()
214 static void wa_add(struct i915_wa_list *wal, i915_reg_t reg, in wa_add() argument
225 _wa_add(wal, &wa); in wa_add()
228 static void wa_mcr_add(struct i915_wa_list *wal, i915_mcr_reg_t reg, in wa_mcr_add() argument
240 _wa_add(wal, &wa); in wa_mcr_add()
244 wa_write_clr_set(struct i915_wa_list *wal, i915_reg_t reg, u32 clear, u32 set) in wa_write_clr_set() argument
246 wa_add(wal, reg, clear, set, clear | set, false); in wa_write_clr_set()
250 wa_mcr_write_clr_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clear, u32 set) in wa_mcr_write_clr_set() argument
252 wa_mcr_add(wal, reg, clear, set, clear | set, false); in wa_mcr_write_clr_set()
256 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 set) in wa_write() argument
258 wa_write_clr_set(wal, reg, ~0, set); in wa_write()
262 wa_mcr_write(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) in wa_mcr_write() argument
264 wa_mcr_write_clr_set(wal, reg, ~0, set); in wa_mcr_write()
268 wa_write_or(struct i915_wa_list *wal, i915_reg_t reg, u32 set) in wa_write_or() argument
270 wa_write_clr_set(wal, reg, set, set); in wa_write_or()
274 wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) in wa_mcr_write_or() argument
276 wa_mcr_write_clr_set(wal, reg, set, set); in wa_mcr_write_or()
280 wa_write_clr(struct i915_wa_list *wal, i915_reg_t reg, u32 clr) in wa_write_clr() argument
282 wa_write_clr_set(wal, reg, clr, 0); in wa_write_clr()
286 wa_mcr_write_clr(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 clr) in wa_mcr_write_clr() argument
288 wa_mcr_write_clr_set(wal, reg, clr, 0); in wa_mcr_write_clr()
303 wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val) in wa_masked_en() argument
305 wa_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_masked_en()
309 wa_mcr_masked_en(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) in wa_mcr_masked_en() argument
311 wa_mcr_add(wal, reg, 0, _MASKED_BIT_ENABLE(val), val, true); in wa_mcr_masked_en()
315 wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val) in wa_masked_dis() argument
317 wa_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_masked_dis()
321 wa_mcr_masked_dis(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 val) in wa_mcr_masked_dis() argument
323 wa_mcr_add(wal, reg, 0, _MASKED_BIT_DISABLE(val), val, true); in wa_mcr_masked_dis()
327 wa_masked_field_set(struct i915_wa_list *wal, i915_reg_t reg, in wa_masked_field_set() argument
330 wa_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_masked_field_set()
334 wa_mcr_masked_field_set(struct i915_wa_list *wal, i915_mcr_reg_t reg, in wa_mcr_masked_field_set() argument
337 wa_mcr_add(wal, reg, 0, _MASKED_FIELD(mask, val), mask, true); in wa_mcr_masked_field_set()
341 struct i915_wa_list *wal) in gen6_ctx_workarounds_init() argument
343 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen6_ctx_workarounds_init()
347 struct i915_wa_list *wal) in gen7_ctx_workarounds_init() argument
349 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen7_ctx_workarounds_init()
353 struct i915_wa_list *wal) in gen8_ctx_workarounds_init() argument
355 wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING); in gen8_ctx_workarounds_init()
358 wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE); in gen8_ctx_workarounds_init()
361 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, in gen8_ctx_workarounds_init()
370 wa_masked_en(wal, HDC_CHICKEN0, in gen8_ctx_workarounds_init()
382 wa_masked_dis(wal, CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); in gen8_ctx_workarounds_init()
385 wa_masked_en(wal, CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); in gen8_ctx_workarounds_init()
395 wa_masked_field_set(wal, GEN7_GT_MODE, in gen8_ctx_workarounds_init()
401 struct i915_wa_list *wal) in bdw_ctx_workarounds_init() argument
405 gen8_ctx_workarounds_init(engine, wal); in bdw_ctx_workarounds_init()
408 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); in bdw_ctx_workarounds_init()
415 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, in bdw_ctx_workarounds_init()
418 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, in bdw_ctx_workarounds_init()
421 wa_masked_en(wal, HDC_CHICKEN0, in bdw_ctx_workarounds_init()
429 struct i915_wa_list *wal) in chv_ctx_workarounds_init() argument
431 gen8_ctx_workarounds_init(engine, wal); in chv_ctx_workarounds_init()
434 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE); in chv_ctx_workarounds_init()
437 wa_masked_en(wal, HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); in chv_ctx_workarounds_init()
441 struct i915_wa_list *wal) in gen9_ctx_workarounds_init() argument
451 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in gen9_ctx_workarounds_init()
453 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, in gen9_ctx_workarounds_init()
459 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, in gen9_ctx_workarounds_init()
465 wa_mcr_masked_en(wal, GEN9_HALF_SLICE_CHICKEN7, in gen9_ctx_workarounds_init()
471 wa_masked_en(wal, CACHE_MODE_1, in gen9_ctx_workarounds_init()
476 wa_mcr_masked_dis(wal, GEN9_HALF_SLICE_CHICKEN5, in gen9_ctx_workarounds_init()
480 wa_masked_en(wal, HDC_CHICKEN0, in gen9_ctx_workarounds_init()
498 wa_masked_en(wal, HDC_CHICKEN0, in gen9_ctx_workarounds_init()
506 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN3, in gen9_ctx_workarounds_init()
510 wa_mcr_masked_en(wal, HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE); in gen9_ctx_workarounds_init()
524 wa_masked_dis(wal, GEN8_CS_CHICKEN1, GEN9_PREEMPT_3D_OBJECT_LEVEL); in gen9_ctx_workarounds_init()
527 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, in gen9_ctx_workarounds_init()
533 wa_masked_en(wal, GEN9_WM_CHICKEN3, GEN9_FACTOR_IN_CLR_VAL_HIZ); in gen9_ctx_workarounds_init()
537 struct i915_wa_list *wal) in skl_tune_iz_hashing() argument
567 wa_masked_field_set(wal, GEN7_GT_MODE, in skl_tune_iz_hashing()
577 struct i915_wa_list *wal) in skl_ctx_workarounds_init() argument
579 gen9_ctx_workarounds_init(engine, wal); in skl_ctx_workarounds_init()
580 skl_tune_iz_hashing(engine, wal); in skl_ctx_workarounds_init()
584 struct i915_wa_list *wal) in bxt_ctx_workarounds_init() argument
586 gen9_ctx_workarounds_init(engine, wal); in bxt_ctx_workarounds_init()
589 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN, in bxt_ctx_workarounds_init()
593 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in bxt_ctx_workarounds_init()
598 struct i915_wa_list *wal) in kbl_ctx_workarounds_init() argument
602 gen9_ctx_workarounds_init(engine, wal); in kbl_ctx_workarounds_init()
606 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in kbl_ctx_workarounds_init()
610 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, in kbl_ctx_workarounds_init()
615 struct i915_wa_list *wal) in glk_ctx_workarounds_init() argument
617 gen9_ctx_workarounds_init(engine, wal); in glk_ctx_workarounds_init()
620 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in glk_ctx_workarounds_init()
625 struct i915_wa_list *wal) in cfl_ctx_workarounds_init() argument
627 gen9_ctx_workarounds_init(engine, wal); in cfl_ctx_workarounds_init()
630 wa_masked_en(wal, COMMON_SLICE_CHICKEN2, in cfl_ctx_workarounds_init()
634 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, in cfl_ctx_workarounds_init()
639 struct i915_wa_list *wal) in icl_ctx_workarounds_init() argument
642 wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL); in icl_ctx_workarounds_init()
651 wa_mcr_masked_en(wal, ICL_HDC_MODE, HDC_FORCE_NON_COHERENT); in icl_ctx_workarounds_init()
654 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in icl_ctx_workarounds_init()
660 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, in icl_ctx_workarounds_init()
665 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, in icl_ctx_workarounds_init()
669 wa_write(wal, IVB_FBC_RT_BASE, 0xFFFFFFFF & ~ILK_FBC_RT_VALID); in icl_ctx_workarounds_init()
670 wa_write_clr_set(wal, IVB_FBC_RT_BASE_UPPER, in icl_ctx_workarounds_init()
675 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU); in icl_ctx_workarounds_init()
683 struct i915_wa_list *wal) in dg2_ctx_gt_tuning_init() argument
685 wa_mcr_masked_en(wal, CHICKEN_RASTER_2, TBIMR_FAST_CLIP); in dg2_ctx_gt_tuning_init()
686 wa_mcr_write_clr_set(wal, XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK, in dg2_ctx_gt_tuning_init()
688 wa_mcr_write_clr_set(wal, XEHP_FF_MODE2, FF_MODE2_TDS_TIMER_MASK, in dg2_ctx_gt_tuning_init()
693 struct i915_wa_list *wal) in gen12_ctx_workarounds_init() argument
709 wa_masked_en(wal, GEN11_COMMON_SLICE_CHICKEN3, in gen12_ctx_workarounds_init()
713 wa_masked_field_set(wal, GEN8_CS_CHICKEN1, in gen12_ctx_workarounds_init()
735 wa_add(wal, in gen12_ctx_workarounds_init()
743 wa_masked_en(wal, HIZ_CHICKEN, HZ_DEPTH_TEST_LE_GE_OPT_DISABLE); in gen12_ctx_workarounds_init()
746 wa_masked_en(wal, COMMON_SLICE_CHICKEN4, DISABLE_TDC_LOAD_BALANCING_CALC); in gen12_ctx_workarounds_init()
751 struct i915_wa_list *wal) in dg1_ctx_workarounds_init() argument
753 gen12_ctx_workarounds_init(engine, wal); in dg1_ctx_workarounds_init()
756 wa_masked_dis(wal, GEN11_COMMON_SLICE_CHICKEN3, in dg1_ctx_workarounds_init()
760 wa_masked_en(wal, HIZ_CHICKEN, in dg1_ctx_workarounds_init()
765 struct i915_wa_list *wal) in dg2_ctx_workarounds_init() argument
767 dg2_ctx_gt_tuning_init(engine, wal); in dg2_ctx_workarounds_init()
770 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, in dg2_ctx_workarounds_init()
774 wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000); in dg2_ctx_workarounds_init()
777 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); in dg2_ctx_workarounds_init()
780 wa_mcr_masked_en(wal, CHICKEN_RASTER_1, DIS_SF_ROUND_NEAREST_EVEN); in dg2_ctx_workarounds_init()
783 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); in dg2_ctx_workarounds_init()
787 struct i915_wa_list *wal) in xelpg_ctx_gt_tuning_init() argument
791 dg2_ctx_gt_tuning_init(engine, wal); in xelpg_ctx_gt_tuning_init()
800 wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false); in xelpg_ctx_gt_tuning_init()
804 struct i915_wa_list *wal) in xelpg_ctx_workarounds_init() argument
808 xelpg_ctx_gt_tuning_init(engine, wal); in xelpg_ctx_workarounds_init()
813 wa_masked_field_set(wal, VF_PREEMPTION, in xelpg_ctx_workarounds_init()
817 wa_mcr_masked_en(wal, XEHP_SLICE_COMMON_ECO_CHICKEN1, in xelpg_ctx_workarounds_init()
821 wa_mcr_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS); in xelpg_ctx_workarounds_init()
824 wa_mcr_masked_en(wal, XEHP_PSS_MODE2, SCOREBOARD_STALL_FLUSH_CONTROL); in xelpg_ctx_workarounds_init()
828 wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE); in xelpg_ctx_workarounds_init()
832 struct i915_wa_list *wal) in fakewa_disable_nestedbb_mode() argument
859 wa_masked_dis(wal, RING_MI_MODE(engine->mmio_base), TGL_NESTED_BB_EN); in fakewa_disable_nestedbb_mode()
863 struct i915_wa_list *wal) in gen12_ctx_gt_mocs_init() argument
874 wa_write_clr_set(wal, in gen12_ctx_gt_mocs_init()
889 struct i915_wa_list *wal) in gen12_ctx_gt_fake_wa_init() argument
892 fakewa_disable_nestedbb_mode(engine, wal); in gen12_ctx_gt_fake_wa_init()
894 gen12_ctx_gt_mocs_init(engine, wal); in gen12_ctx_gt_fake_wa_init()
899 struct i915_wa_list *wal, in __intel_engine_init_ctx_wa() argument
904 wa_init_start(wal, engine->gt, name, engine->name); in __intel_engine_init_ctx_wa()
912 gen12_ctx_gt_fake_wa_init(engine, wal); in __intel_engine_init_ctx_wa()
918 xelpg_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
922 dg2_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
926 dg1_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
928 gen12_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
930 icl_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
932 cfl_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
934 glk_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
936 kbl_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
938 bxt_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
940 skl_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
942 chv_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
944 bdw_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
946 gen7_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
948 gen6_ctx_workarounds_init(engine, wal); in __intel_engine_init_ctx_wa()
955 wa_init_finish(wal); in __intel_engine_init_ctx_wa()
965 struct i915_wa_list *wal = &rq->engine->ctx_wa_list; in intel_engine_emit_ctx_wa() local
974 if (wal->count == 0) in intel_engine_emit_ctx_wa()
981 cs = intel_ring_begin(rq, (wal->count * 2 + 2)); in intel_engine_emit_ctx_wa()
985 fw = wal_get_fw_for_rmw(uncore, wal); in intel_engine_emit_ctx_wa()
987 intel_gt_mcr_lock(wal->gt, &flags); in intel_engine_emit_ctx_wa()
991 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); in intel_engine_emit_ctx_wa()
992 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in intel_engine_emit_ctx_wa()
1000 intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) : in intel_engine_emit_ctx_wa()
1013 intel_gt_mcr_unlock(wal->gt, flags); in intel_engine_emit_ctx_wa()
1026 struct i915_wa_list *wal) in gen4_gt_workarounds_init() argument
1029 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in gen4_gt_workarounds_init()
1033 g4x_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in g4x_gt_workarounds_init() argument
1035 gen4_gt_workarounds_init(gt, wal); in g4x_gt_workarounds_init()
1038 wa_masked_en(wal, CACHE_MODE_0, CM0_PIPELINED_RENDER_FLUSH_DISABLE); in g4x_gt_workarounds_init()
1042 ilk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in ilk_gt_workarounds_init() argument
1044 g4x_gt_workarounds_init(gt, wal); in ilk_gt_workarounds_init()
1046 wa_masked_en(wal, _3D_CHICKEN2, _3D_CHICKEN2_WM_READ_PIPELINED); in ilk_gt_workarounds_init()
1050 snb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in snb_gt_workarounds_init() argument
1055 ivb_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in ivb_gt_workarounds_init() argument
1058 wa_masked_dis(wal, in ivb_gt_workarounds_init()
1063 wa_write(wal, GEN7_L3CNTLREG1, GEN7_WA_FOR_GEN7_L3_CONTROL); in ivb_gt_workarounds_init()
1064 wa_write(wal, GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); in ivb_gt_workarounds_init()
1067 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); in ivb_gt_workarounds_init()
1071 vlv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in vlv_gt_workarounds_init() argument
1074 wa_write_clr(wal, GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); in vlv_gt_workarounds_init()
1080 wa_write(wal, GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); in vlv_gt_workarounds_init()
1084 hsw_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in hsw_gt_workarounds_init() argument
1087 wa_write(wal, HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); in hsw_gt_workarounds_init()
1089 wa_add(wal, in hsw_gt_workarounds_init()
1095 wa_write_clr(wal, GEN7_FF_THREAD_MODE, GEN7_FF_VS_REF_CNT_FFME); in hsw_gt_workarounds_init()
1099 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal) in gen9_wa_init_mcr() argument
1133 wa_write_clr_set(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr); in gen9_wa_init_mcr()
1137 gen9_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in gen9_gt_workarounds_init() argument
1142 gen9_wa_init_mcr(i915, wal); in gen9_gt_workarounds_init()
1146 wa_write_or(wal, in gen9_gt_workarounds_init()
1156 wa_write_or(wal, in gen9_gt_workarounds_init()
1162 wa_write_or(wal, in gen9_gt_workarounds_init()
1168 skl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in skl_gt_workarounds_init() argument
1170 gen9_gt_workarounds_init(gt, wal); in skl_gt_workarounds_init()
1173 wa_write_or(wal, in skl_gt_workarounds_init()
1179 wa_write_or(wal, in skl_gt_workarounds_init()
1185 kbl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in kbl_gt_workarounds_init() argument
1187 gen9_gt_workarounds_init(gt, wal); in kbl_gt_workarounds_init()
1191 wa_write_or(wal, in kbl_gt_workarounds_init()
1196 wa_write_or(wal, in kbl_gt_workarounds_init()
1201 wa_write_or(wal, in kbl_gt_workarounds_init()
1207 glk_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in glk_gt_workarounds_init() argument
1209 gen9_gt_workarounds_init(gt, wal); in glk_gt_workarounds_init()
1213 cfl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in cfl_gt_workarounds_init() argument
1215 gen9_gt_workarounds_init(gt, wal); in cfl_gt_workarounds_init()
1218 wa_write_or(wal, in cfl_gt_workarounds_init()
1223 wa_write_or(wal, in cfl_gt_workarounds_init()
1228 static void __set_mcr_steering(struct i915_wa_list *wal, in __set_mcr_steering() argument
1237 wa_write_clr_set(wal, steering_reg, mcr_mask, mcr); in __set_mcr_steering()
1248 static void __add_mcr_wa(struct intel_gt *gt, struct i915_wa_list *wal, in __add_mcr_wa() argument
1251 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); in __add_mcr_wa()
1260 icl_wa_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) in icl_wa_init_mcr() argument
1287 __add_mcr_wa(gt, wal, 0, subslice); in icl_wa_init_mcr()
1291 xehp_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) in xehp_init_mcr() argument
1357 __add_mcr_wa(gt, wal, slice, subslice); in xehp_init_mcr()
1368 __set_mcr_steering(wal, MCFG_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1369 __set_mcr_steering(wal, SF_MCR_SELECTOR, 0, 2); in xehp_init_mcr()
1376 __set_mcr_steering(wal, GAM_MCR_SELECTOR, 1, 0); in xehp_init_mcr()
1380 pvc_init_mcr(struct intel_gt *gt, struct i915_wa_list *wal) in pvc_init_mcr() argument
1390 __add_mcr_wa(gt, wal, dss / GEN_DSS_PER_CSLICE, dss % GEN_DSS_PER_CSLICE); in pvc_init_mcr()
1394 icl_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in icl_gt_workarounds_init() argument
1398 icl_wa_init_mcr(gt, wal); in icl_gt_workarounds_init()
1401 wa_write_clr_set(wal, in icl_gt_workarounds_init()
1409 wa_write_or(wal, in icl_gt_workarounds_init()
1417 wa_write_or(wal, in icl_gt_workarounds_init()
1424 wa_write_or(wal, in icl_gt_workarounds_init()
1432 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, in icl_gt_workarounds_init()
1436 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, in icl_gt_workarounds_init()
1440 wa_mcr_write_or(wal, in icl_gt_workarounds_init()
1448 wa_write_or(wal, in icl_gt_workarounds_init()
1456 wa_mcr_write_clr(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); in icl_gt_workarounds_init()
1466 wa_14011060649(struct intel_gt *gt, struct i915_wa_list *wal) in wa_14011060649() argument
1476 wa_write_or(wal, VDBOX_CGCTL3F10(engine->mmio_base), in wa_14011060649()
1482 gen12_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in gen12_gt_workarounds_init() argument
1484 icl_wa_init_mcr(gt, wal); in gen12_gt_workarounds_init()
1487 wa_14011060649(gt, wal); in gen12_gt_workarounds_init()
1490 wa_mcr_write_or(wal, GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE); in gen12_gt_workarounds_init()
1501 wa_add(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE, in gen12_gt_workarounds_init()
1506 dg1_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in dg1_gt_workarounds_init() argument
1508 gen12_gt_workarounds_init(gt, wal); in dg1_gt_workarounds_init()
1511 wa_mcr_write_or(wal, SUBSLICE_UNIT_LEVEL_CLKGATE2, in dg1_gt_workarounds_init()
1516 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL); in dg1_gt_workarounds_init()
1520 xehpsdv_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in xehpsdv_gt_workarounds_init() argument
1524 xehp_init_mcr(gt, wal); in xehpsdv_gt_workarounds_init()
1527 wa_mcr_write_or(wal, SCCGCTL94DC, CG3DDISURB); in xehpsdv_gt_workarounds_init()
1531 wa_mcr_masked_dis(wal, MLTICTXCTL, TDONRENDER); in xehpsdv_gt_workarounds_init()
1532 wa_mcr_write_or(wal, L3SQCREG1_CCS0, FLUSHALLNONCOH); in xehpsdv_gt_workarounds_init()
1537 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, in xehpsdv_gt_workarounds_init()
1542 wa_write_or(wal, UNSLCGCTL9440, GAMTLBOACS_CLKGATE_DIS | in xehpsdv_gt_workarounds_init()
1554 wa_write_or(wal, UNSLCGCTL9444, GAMTLBGFXA0_CLKGATE_DIS | in xehpsdv_gt_workarounds_init()
1573 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, VFUNIT_CLKGATE_DIS); in xehpsdv_gt_workarounds_init()
1576 wa_14011060649(gt, wal); in xehpsdv_gt_workarounds_init()
1579 wa_mcr_write_or(wal, XEHP_MERT_MOD_CTRL, FORCE_MISS_FTLB); in xehpsdv_gt_workarounds_init()
1582 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, in xehpsdv_gt_workarounds_init()
1586 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); in xehpsdv_gt_workarounds_init()
1590 dg2_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in dg2_gt_workarounds_init() argument
1592 xehp_init_mcr(gt, wal); in dg2_gt_workarounds_init()
1595 wa_14011060649(gt, wal); in dg2_gt_workarounds_init()
1599 wa_write_or(wal, UNSLICE_UNIT_LEVEL_CLKGATE, in dg2_gt_workarounds_init()
1603 wa_mcr_write_or(wal, GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE, in dg2_gt_workarounds_init()
1608 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); in dg2_gt_workarounds_init()
1611 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); in dg2_gt_workarounds_init()
1614 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); in dg2_gt_workarounds_init()
1615 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); in dg2_gt_workarounds_init()
1616 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); in dg2_gt_workarounds_init()
1617 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); in dg2_gt_workarounds_init()
1620 wa_mcr_write_or(wal, XEHP_GAMCNTRL_CTRL, in dg2_gt_workarounds_init()
1624 wa_mcr_write_or(wal, XEHP_L3NODEARBCFG, XEHP_LNESPARE); in dg2_gt_workarounds_init()
1628 pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in pvc_gt_workarounds_init() argument
1630 pvc_init_mcr(gt, wal); in pvc_gt_workarounds_init()
1633 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); in pvc_gt_workarounds_init()
1636 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); in pvc_gt_workarounds_init()
1637 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); in pvc_gt_workarounds_init()
1638 wa_mcr_write_or(wal, XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB); in pvc_gt_workarounds_init()
1639 wa_mcr_write_or(wal, XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB); in pvc_gt_workarounds_init()
1642 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC); in pvc_gt_workarounds_init()
1646 xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in xelpg_gt_workarounds_init() argument
1649 wa_mcr_write_or(wal, RENDER_MOD_CTRL, FORCE_MISS_FTLB); in xelpg_gt_workarounds_init()
1650 wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB); in xelpg_gt_workarounds_init()
1653 wa_write_or(wal, GEN12_SQCNT1, GEN12_STRICT_RAR_ENABLE); in xelpg_gt_workarounds_init()
1658 wa_mcr_write_clr(wal, SARB_CHICKEN1, COMP_CKN_IN); in xelpg_gt_workarounds_init()
1661 wa_write_clr(wal, GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE); in xelpg_gt_workarounds_init()
1672 xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) in xelpmp_gt_workarounds_init() argument
1681 wa_write_or(wal, XELPMP_GSC_MOD_CTRL, FORCE_MISS_FTLB); in xelpmp_gt_workarounds_init()
1697 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal) in gt_tuning_settings() argument
1700 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); in gt_tuning_settings()
1701 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); in gt_tuning_settings()
1705 wa_mcr_write(wal, XEHPC_L3SCRUB, in gt_tuning_settings()
1707 wa_mcr_masked_en(wal, XEHPC_LNCFMISCCFGREG0, XEHPC_HOSTCACHEEN); in gt_tuning_settings()
1711 wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS); in gt_tuning_settings()
1712 wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS); in gt_tuning_settings()
1717 gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) in gt_init_workarounds() argument
1721 gt_tuning_settings(gt, wal); in gt_init_workarounds()
1725 xelpmp_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1733 xelpg_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1735 pvc_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1737 dg2_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1739 xehpsdv_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1741 dg1_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1743 gen12_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1745 icl_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1747 cfl_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1749 glk_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1751 kbl_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1753 gen9_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1755 skl_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1757 hsw_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1759 vlv_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1761 ivb_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1763 snb_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1765 ilk_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1767 g4x_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1769 gen4_gt_workarounds_init(gt, wal); in gt_init_workarounds()
1778 struct i915_wa_list *wal = >->wa_list; in intel_gt_init_workarounds() local
1780 wa_init_start(wal, gt, "GT", "global"); in intel_gt_init_workarounds()
1781 gt_init_workarounds(gt, wal); in intel_gt_init_workarounds()
1782 wa_init_finish(wal); in intel_gt_init_workarounds()
1801 static void wa_list_apply(const struct i915_wa_list *wal) in wa_list_apply() argument
1803 struct intel_gt *gt = wal->gt; in wa_list_apply()
1810 if (!wal->count) in wa_list_apply()
1813 fw = wal_get_fw_for_rmw(uncore, wal); in wa_list_apply()
1819 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_apply()
1840 wa_verify(gt, wa, val, wal->name, "application"); in wa_list_apply()
1855 const struct i915_wa_list *wal, in wa_list_verify() argument
1865 fw = wal_get_fw_for_rmw(uncore, wal); in wa_list_verify()
1871 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in wa_list_verify()
1872 ok &= wa_verify(wal->gt, wa, wa->is_mcr ? in wa_list_verify()
1875 wal->name, from); in wa_list_verify()
1905 whitelist_reg_ext(struct i915_wa_list *wal, i915_reg_t reg, u32 flags) in whitelist_reg_ext() argument
1911 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) in whitelist_reg_ext()
1918 _wa_add(wal, &wa); in whitelist_reg_ext()
1922 whitelist_mcr_reg_ext(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 flags) in whitelist_mcr_reg_ext() argument
1929 if (GEM_DEBUG_WARN_ON(wal->count >= RING_MAX_NONPRIV_SLOTS)) in whitelist_mcr_reg_ext()
1936 _wa_add(wal, &wa); in whitelist_mcr_reg_ext()
1940 whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) in whitelist_reg() argument
1942 whitelist_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); in whitelist_reg()
1946 whitelist_mcr_reg(struct i915_wa_list *wal, i915_mcr_reg_t reg) in whitelist_mcr_reg() argument
1948 whitelist_mcr_reg_ext(wal, reg, RING_FORCE_TO_NONPRIV_ACCESS_RW); in whitelist_mcr_reg()
2239 const struct i915_wa_list *wal = &engine->whitelist; in intel_engine_apply_whitelist() local
2245 if (!wal->count) in intel_engine_apply_whitelist()
2248 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) in intel_engine_apply_whitelist()
2268 engine_fake_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in engine_fake_wa_init() argument
2297 wa_masked_field_set(wal, in engine_fake_wa_init()
2305 rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in rcs_engine_wa_init() argument
2313 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, in rcs_engine_wa_init()
2321 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, in rcs_engine_wa_init()
2328 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, in rcs_engine_wa_init()
2337 wa_mcr_masked_dis(wal, XEHP_HDC_CHICKEN0, in rcs_engine_wa_init()
2343 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in rcs_engine_wa_init()
2357 wa_masked_en(wal, in rcs_engine_wa_init()
2365 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ); in rcs_engine_wa_init()
2373 wa_write_or(wal, GEN7_FF_THREAD_MODE, in rcs_engine_wa_init()
2377 wa_mcr_masked_en(wal, in rcs_engine_wa_init()
2385 wa_mcr_masked_en(wal, GEN8_ROW_CHICKEN2, in rcs_engine_wa_init()
2389 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH); in rcs_engine_wa_init()
2400 wa_masked_en(wal, in rcs_engine_wa_init()
2408 wa_masked_en(wal, in rcs_engine_wa_init()
2416 wa_write_or(wal, in rcs_engine_wa_init()
2424 wa_write_clr_set(wal, in rcs_engine_wa_init()
2428 wa_write_clr_set(wal, in rcs_engine_wa_init()
2437 wa_mcr_write_or(wal, in rcs_engine_wa_init()
2442 wa_write_or(wal, in rcs_engine_wa_init()
2447 wa_mcr_write_clr_set(wal, in rcs_engine_wa_init()
2453 wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, in rcs_engine_wa_init()
2460 wa_write_or(wal, in rcs_engine_wa_init()
2465 wa_masked_en(wal, in rcs_engine_wa_init()
2525 wa_masked_en(wal, in rcs_engine_wa_init()
2534 wa_write_or(wal, in rcs_engine_wa_init()
2541 wa_masked_en(wal, in rcs_engine_wa_init()
2548 wa_masked_en(wal, in rcs_engine_wa_init()
2553 wa_mcr_write_or(wal, in rcs_engine_wa_init()
2559 wa_mcr_write_clr_set(wal, in rcs_engine_wa_init()
2566 wa_mcr_write_or(wal, in rcs_engine_wa_init()
2571 wa_write_clr_set(wal, GEN9_SCRATCH_LNCF1, in rcs_engine_wa_init()
2573 wa_mcr_write_clr_set(wal, GEN8_L3SQCREG4, in rcs_engine_wa_init()
2575 wa_mcr_write_clr_set(wal, GEN9_SCRATCH1, in rcs_engine_wa_init()
2581 wa_masked_en(wal, in rcs_engine_wa_init()
2584 wa_masked_dis(wal, in rcs_engine_wa_init()
2592 wa_masked_en(wal, in rcs_engine_wa_init()
2602 wa_write_clr_set(wal, in rcs_engine_wa_init()
2611 wa_masked_en(wal, in rcs_engine_wa_init()
2619 wa_masked_en(wal, in rcs_engine_wa_init()
2625 wa_masked_dis(wal, in rcs_engine_wa_init()
2636 wa_write_clr_set(wal, in rcs_engine_wa_init()
2645 wa_masked_en(wal, in rcs_engine_wa_init()
2652 wa_masked_en(wal, in rcs_engine_wa_init()
2657 wa_masked_dis(wal, CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); in rcs_engine_wa_init()
2664 wa_masked_en(wal, in rcs_engine_wa_init()
2676 wa_masked_field_set(wal, in rcs_engine_wa_init()
2690 wa_masked_en(wal, in rcs_engine_wa_init()
2700 wa_masked_en(wal, in rcs_engine_wa_init()
2705 wa_masked_en(wal, in rcs_engine_wa_init()
2709 wa_masked_en(wal, in rcs_engine_wa_init()
2729 wa_masked_field_set(wal, in rcs_engine_wa_init()
2735 wa_masked_dis(wal, CACHE_MODE_0, RC_OP_FLUSH_ENABLE); in rcs_engine_wa_init()
2743 wa_masked_dis(wal, in rcs_engine_wa_init()
2750 wa_add(wal, RING_MI_MODE(RENDER_RING_BASE), in rcs_engine_wa_init()
2766 wa_add(wal, ECOSKPD(RENDER_RING_BASE), in rcs_engine_wa_init()
2773 xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in xcs_engine_wa_init() argument
2779 wa_write(wal, in xcs_engine_wa_init()
2786 ccs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in ccs_engine_wa_init() argument
2790 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, DISABLE_ECC); in ccs_engine_wa_init()
2808 struct i915_wa_list *wal) in add_render_compute_tuning_settings() argument
2813 wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512); in add_render_compute_tuning_settings()
2821 wa_mcr_masked_field_set(wal, GEN9_ROW_CHICKEN4, THREAD_EX_ARB_MODE, in add_render_compute_tuning_settings()
2825 wa_write_clr(wal, GEN8_GARBCNTL, GEN12_BUS_HASH_CTL_BIT_EXC); in add_render_compute_tuning_settings()
2828 static void ccs_engine_wa_mode(struct intel_engine_cs *engine, struct i915_wa_list *wal) in ccs_engine_wa_mode() argument
2842 wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE); in ccs_engine_wa_mode()
2849 wa_masked_en(wal, XEHP_CCS_MODE, mode); in ccs_engine_wa_mode()
2862 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) in general_render_compute_wa_init() argument
2867 add_render_compute_tuning_settings(gt, wal); in general_render_compute_wa_init()
2883 wa_mcr_masked_en(wal, in general_render_compute_wa_init()
2892 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); in general_render_compute_wa_init()
2900 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, in general_render_compute_wa_init()
2905 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, in general_render_compute_wa_init()
2912 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, in general_render_compute_wa_init()
2916 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); in general_render_compute_wa_init()
2924 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); in general_render_compute_wa_init()
2929 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); in general_render_compute_wa_init()
2932 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); in general_render_compute_wa_init()
2940 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); in general_render_compute_wa_init()
2948 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, in general_render_compute_wa_init()
2953 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, in general_render_compute_wa_init()
2963 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, in general_render_compute_wa_init()
2971 wa_mcr_masked_en(wal, in general_render_compute_wa_init()
2976 wa_mcr_masked_en(wal, in general_render_compute_wa_init()
2981 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, in general_render_compute_wa_init()
2987 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal) in engine_init_workarounds() argument
2992 engine_fake_wa_init(engine, wal); in engine_init_workarounds()
3000 general_render_compute_wa_init(engine, wal); in engine_init_workarounds()
3001 ccs_engine_wa_mode(engine, wal); in engine_init_workarounds()
3005 ccs_engine_wa_init(engine, wal); in engine_init_workarounds()
3007 rcs_engine_wa_init(engine, wal); in engine_init_workarounds()
3009 xcs_engine_wa_init(engine, wal); in engine_init_workarounds()
3014 struct i915_wa_list *wal = &engine->wa_list; in intel_engine_init_workarounds() local
3016 wa_init_start(wal, engine->gt, "engine", engine->name); in intel_engine_init_workarounds()
3017 engine_init_workarounds(engine, wal); in intel_engine_init_workarounds()
3018 wa_init_finish(wal); in intel_engine_init_workarounds()
3090 const struct i915_wa_list *wal, in wa_list_srm() argument
3102 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
3111 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in wa_list_srm()
3128 const struct i915_wa_list * const wal, in engine_wa_list_verify() argument
3139 if (!wal->count) in engine_wa_list_verify()
3143 wal->count * sizeof(u32)); in engine_wa_list_verify()
3169 err = wa_list_srm(rq, wal, vma); in engine_wa_list_verify()
3191 for (i = 0, wa = wal->list; i < wal->count; i++, wa++) { in engine_wa_list_verify()
3195 if (!wa_verify(wal->gt, wa, results[i], wal->name, from)) in engine_wa_list_verify()