433 	u16 rgvswctl;  in __gen5_rps_set()  local
437 	rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);  in __gen5_rps_set()
438 	if (rgvswctl & MEMCTL_CMD_STS) {  in __gen5_rps_set()
447 	rgvswctl =  in __gen5_rps_set()
451 	intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);  in __gen5_rps_set()
454 	rgvswctl |= MEMCTL_CMD_STS;  in __gen5_rps_set()
455 	intel_uncore_write16(uncore, MEMSWCTL, rgvswctl);  in __gen5_rps_set()
624 	u16 rgvswctl;  in gen5_rps_disable()  local
632 	rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);  in gen5_rps_disable()
641 	rgvswctl |= MEMCTL_CMD_STS;  in gen5_rps_disable()
642 	intel_uncore_write(uncore, MEMSWCTL, rgvswctl);  in gen5_rps_disable()