i915/gt/intel_mocs.c

75 /* L3 caching options */
110  * PTE and those platforms except TGL/RKL will be initialized L3 WB to
124  *       indices have been set to L3 WB. These reserved entries should never
127  *       For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
145 	 * - used by the L3 for all of its evictions.
148 	 * - used to force L3 uncachable cycles.
149 	 *   Thus it is expected to make the surface L3 uncacheable.
166 	/* Base - L3 + LLC */ \
174 	/* Base - L3 */ \
186 	/* Age 0 - L3 + LLC */ \
194 	/* Age: Don't Chg. - L3 + LLC */ \
202 	/* No AOM - L3 + LLC */ \
210 	/* No AOM; Age 0 - L3 + LLC */ \
218 	/* No AOM; Age:DC - L3 + LLC */ \
226 	/* Bypass LLC - L3 (Read-Only) (EHL+) */ \
230 	/* Self-Snoop - L3 + LLC */ \
234 	/* Skip Caching - L3 + LLC(12.5%) */ \
238 	/* Skip Caching - L3 + LLC(25%) */ \
242 	/* Skip Caching - L3 + LLC(50%) */ \
246 	/* Skip Caching - L3 + LLC(75%) */ \
250 	/* Skip Caching - L3 + LLC(87.5%) */ \
266 	 * Reserved and unspecified MOCS indices have been set to (L3 + LCC).
278 	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
282 	/* Implicitly enable L1 - HDC:L1 + L3 */
309 	/* Base - L3 + LeCC:PAT (Deprecated) */
321 	/* WB - L3 */
323 	/* WB - L3 50% */
325 	/* WB - L3 25% */
327 	/* WB - L3 12.5% */
330 	/* HDC:L1 + L3 */
344 	/* Implicitly enable L1 - HDC:L1 + L3 + LLC */
348 	/* Implicitly enable L1 - HDC:L1 + L3 */
374 	/* UC - Coherent; GO:L3 */
380 	/* UC - Non-Coherent; GO:L3 */
396 	/* UC - Coherent; GO:L3 */
423 	/* Cached - L3 + L4 */
427 	/* L4 - GO:L3 */
431 	/* Uncached - GO:L3 */
443 	/* L4 - L3:NoLKUP; GO:L3 */
447 	/* Uncached - L3:NoLKUP; GO:L3 */
451 	/* L4 - L3:NoLKUP; GO:Mem */
455 	/* Uncached - L3:NoLKUP; GO:Mem */
459 	/* Display - L3; L4:WT */