Lines Matching defs:i
296 #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ argument
994 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ argument
995 #define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4) argument
1009 #define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4) argument
1069 #define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4) argument
1071 #define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4) argument
1073 #define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4) argument
1075 #define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4) argument
1077 #define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4) argument
1249 #define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4) argument
1432 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ argument
1433 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ argument
1460 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ argument
1461 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ argument
1519 #define GEN7_GT_SCRATCH(i) _MMIO(0x4f100 + (i) * 4) argument