Lines Matching full:gt
12 * DOC: GT Multicast/Replicated (MCR) Register Support
14 * Some GT registers are designed as "multicast" or "replicated" registers:
140 void intel_gt_mcr_init(struct intel_gt *gt) in intel_gt_mcr_init() argument
142 struct drm_i915_private *i915 = gt->i915; in intel_gt_mcr_init()
146 spin_lock_init(>->mcr_lock); in intel_gt_mcr_init()
153 gt->info.mslice_mask = in intel_gt_mcr_init()
154 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, in intel_gt_mcr_init()
156 gt->info.mslice_mask |= in intel_gt_mcr_init()
157 (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
160 if (!gt->info.mslice_mask) /* should be impossible! */ in intel_gt_mcr_init()
161 gt_warn(gt, "mslice mask all zero!\n"); in intel_gt_mcr_init()
164 if (MEDIA_VER(i915) >= 13 && gt->type == GT_MEDIA) { in intel_gt_mcr_init()
165 gt->steering_table[OADDRM] = xelpmp_oaddrm_steering_table; in intel_gt_mcr_init()
168 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || in intel_gt_mcr_init()
169 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) in intel_gt_mcr_init()
171 intel_uncore_read(gt->uncore, in intel_gt_mcr_init()
175 intel_uncore_read(gt->uncore, XEHP_FUSE4)); in intel_gt_mcr_init()
182 gt->info.l3bank_mask |= 0x3 << 2 * i; in intel_gt_mcr_init()
184 gt->steering_table[INSTANCE0] = xelpg_instance0_steering_table; in intel_gt_mcr_init()
185 gt->steering_table[L3BANK] = xelpg_l3bank_steering_table; in intel_gt_mcr_init()
186 gt->steering_table[DSS] = xelpg_dss_steering_table; in intel_gt_mcr_init()
188 gt->steering_table[INSTANCE0] = pvc_instance0_steering_table; in intel_gt_mcr_init()
190 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; in intel_gt_mcr_init()
191 gt->steering_table[LNCF] = dg2_lncf_steering_table; in intel_gt_mcr_init()
198 gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table; in intel_gt_mcr_init()
199 gt->steering_table[LNCF] = xehpsdv_lncf_steering_table; in intel_gt_mcr_init()
200 gt->steering_table[GAM] = xehpsdv_gam_steering_table; in intel_gt_mcr_init()
203 gt->steering_table[L3BANK] = icl_l3bank_steering_table; in intel_gt_mcr_init()
204 gt->info.l3bank_mask = in intel_gt_mcr_init()
205 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
207 if (!gt->info.l3bank_mask) /* should be impossible! */ in intel_gt_mcr_init()
208 gt_warn(gt, "L3 bank mask is all zero!\n"); in intel_gt_mcr_init()
233 * @gt: GT to read register from
245 static u32 rw_with_mcr_steering_fw(struct intel_gt *gt, in rw_with_mcr_steering_fw() argument
249 struct intel_uncore *uncore = gt->uncore; in rw_with_mcr_steering_fw()
252 lockdep_assert_held(>->mcr_lock); in rw_with_mcr_steering_fw()
322 static u32 rw_with_mcr_steering(struct intel_gt *gt, in rw_with_mcr_steering() argument
327 struct intel_uncore *uncore = gt->uncore; in rw_with_mcr_steering()
338 intel_gt_mcr_lock(gt, &flags); in rw_with_mcr_steering()
342 val = rw_with_mcr_steering_fw(gt, reg, rw_flag, group, instance, value); in rw_with_mcr_steering()
346 intel_gt_mcr_unlock(gt, flags); in rw_with_mcr_steering()
353 * @gt: GT structure
361 * Context: Takes gt->mcr_lock. uncore->lock should *not* be held when this
365 void intel_gt_mcr_lock(struct intel_gt *gt, unsigned long *flags) in intel_gt_mcr_lock() argument
366 __acquires(>->mcr_lock) in intel_gt_mcr_lock()
371 lockdep_assert_not_held(>->uncore->lock); in intel_gt_mcr_lock()
378 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_lock()
384 * accessed. Grabbing GT forcewake and holding it over the in intel_gt_mcr_lock()
393 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_GT); in intel_gt_mcr_lock()
395 err = wait_for(intel_uncore_read_fw(gt->uncore, in intel_gt_mcr_lock()
405 spin_lock_irqsave(>->mcr_lock, __flags); in intel_gt_mcr_lock()
415 gt_err_ratelimited(gt, "hardware MCR steering semaphore timed out"); in intel_gt_mcr_lock()
416 add_taint_for_CI(gt->i915, TAINT_WARN); /* CI is now unreliable */ in intel_gt_mcr_lock()
422 * @gt: GT structure
427 * Context: Releases gt->mcr_lock
429 void intel_gt_mcr_unlock(struct intel_gt *gt, unsigned long flags) in intel_gt_mcr_unlock() argument
430 __releases(>->mcr_lock) in intel_gt_mcr_unlock()
432 spin_unlock_irqrestore(>->mcr_lock, flags); in intel_gt_mcr_unlock()
434 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_unlock()
435 intel_uncore_write_fw(gt->uncore, MTL_STEER_SEMAPHORE, 0x1); in intel_gt_mcr_unlock()
437 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_GT); in intel_gt_mcr_unlock()
443 * @gt: GT structure
448 * Context: Takes and releases gt->mcr_lock
453 u32 intel_gt_mcr_read(struct intel_gt *gt, in intel_gt_mcr_read() argument
457 return rw_with_mcr_steering(gt, reg, FW_REG_READ, group, instance, 0); in intel_gt_mcr_read()
462 * @gt: GT structure
471 * Context: Calls a function that takes and releases gt->mcr_lock
473 void intel_gt_mcr_unicast_write(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value, in intel_gt_mcr_unicast_write() argument
476 rw_with_mcr_steering(gt, reg, FW_REG_WRITE, group, instance, value); in intel_gt_mcr_unicast_write()
481 * @gt: GT structure
487 * Context: Takes and releases gt->mcr_lock
489 void intel_gt_mcr_multicast_write(struct intel_gt *gt, in intel_gt_mcr_multicast_write() argument
494 intel_gt_mcr_lock(gt, &flags); in intel_gt_mcr_multicast_write()
500 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_multicast_write()
501 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST); in intel_gt_mcr_multicast_write()
503 intel_uncore_write(gt->uncore, mcr_reg_cast(reg), value); in intel_gt_mcr_multicast_write()
505 intel_gt_mcr_unlock(gt, flags); in intel_gt_mcr_multicast_write()
510 * @gt: GT structure
519 * Context: The caller must hold gt->mcr_lock.
521 void intel_gt_mcr_multicast_write_fw(struct intel_gt *gt, i915_mcr_reg_t reg, u32 value) in intel_gt_mcr_multicast_write_fw() argument
523 lockdep_assert_held(>->mcr_lock); in intel_gt_mcr_multicast_write_fw()
529 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) in intel_gt_mcr_multicast_write_fw()
530 intel_uncore_write_fw(gt->uncore, MTL_MCR_SELECTOR, GEN11_MCR_MULTICAST); in intel_gt_mcr_multicast_write_fw()
532 intel_uncore_write_fw(gt->uncore, mcr_reg_cast(reg), value); in intel_gt_mcr_multicast_write_fw()
537 * @gt: GT structure
551 * Context: Calls functions that take and release gt->mcr_lock
555 u32 intel_gt_mcr_multicast_rmw(struct intel_gt *gt, i915_mcr_reg_t reg, in intel_gt_mcr_multicast_rmw() argument
558 u32 val = intel_gt_mcr_read_any(gt, reg); in intel_gt_mcr_multicast_rmw()
560 intel_gt_mcr_multicast_write(gt, reg, (val & ~clear) | set); in intel_gt_mcr_multicast_rmw()
568 * @gt: GT structure
579 static bool reg_needs_read_steering(struct intel_gt *gt, in reg_needs_read_steering() argument
586 if (likely(!gt->steering_table[type])) in reg_needs_read_steering()
590 offset += gt->uncore->gsi_offset; in reg_needs_read_steering()
592 for (entry = gt->steering_table[type]; entry->end; entry++) { in reg_needs_read_steering()
602 * @gt: GT structure
610 static void get_nonterminated_steering(struct intel_gt *gt, in get_nonterminated_steering() argument
619 *instance = __ffs(gt->info.l3bank_mask); in get_nonterminated_steering()
622 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); in get_nonterminated_steering()
623 *group = __ffs(gt->info.mslice_mask); in get_nonterminated_steering()
631 GEM_WARN_ON(!HAS_MSLICE_STEERING(gt->i915)); in get_nonterminated_steering()
632 *group = __ffs(gt->info.mslice_mask) << 1; in get_nonterminated_steering()
636 *group = IS_DG2(gt->i915) ? 1 : 0; in get_nonterminated_steering()
640 dss = intel_sseu_find_first_xehp_dss(>->info.sseu, 0, 0); in get_nonterminated_steering()
653 if ((VDBOX_MASK(gt) | VEBOX_MASK(gt) | gt->info.sfc_mask) & BIT(0)) in get_nonterminated_steering()
669 * @gt: GT structure
679 void intel_gt_mcr_get_nonterminated_steering(struct intel_gt *gt, in intel_gt_mcr_get_nonterminated_steering() argument
686 if (reg_needs_read_steering(gt, reg, type)) { in intel_gt_mcr_get_nonterminated_steering()
687 get_nonterminated_steering(gt, type, group, instance); in intel_gt_mcr_get_nonterminated_steering()
692 *group = gt->default_steering.groupid; in intel_gt_mcr_get_nonterminated_steering()
693 *instance = gt->default_steering.instanceid; in intel_gt_mcr_get_nonterminated_steering()
698 * @gt: GT structure
701 * Reads a GT MCR register. The read will be steered to a non-terminated
707 * Context: The caller must hold gt->mcr_lock.
711 u32 intel_gt_mcr_read_any_fw(struct intel_gt *gt, i915_mcr_reg_t reg) in intel_gt_mcr_read_any_fw() argument
716 lockdep_assert_held(>->mcr_lock); in intel_gt_mcr_read_any_fw()
719 if (reg_needs_read_steering(gt, reg, type)) { in intel_gt_mcr_read_any_fw()
720 get_nonterminated_steering(gt, type, &group, &instance); in intel_gt_mcr_read_any_fw()
721 return rw_with_mcr_steering_fw(gt, reg, in intel_gt_mcr_read_any_fw()
727 return intel_uncore_read_fw(gt->uncore, mcr_reg_cast(reg)); in intel_gt_mcr_read_any_fw()
732 * @gt: GT structure
735 * Reads a GT MCR register. The read will be steered to a non-terminated
738 * Context: Calls a function that takes and releases gt->mcr_lock.
742 u32 intel_gt_mcr_read_any(struct intel_gt *gt, i915_mcr_reg_t reg) in intel_gt_mcr_read_any() argument
748 if (reg_needs_read_steering(gt, reg, type)) { in intel_gt_mcr_read_any()
749 get_nonterminated_steering(gt, type, &group, &instance); in intel_gt_mcr_read_any()
750 return rw_with_mcr_steering(gt, reg, in intel_gt_mcr_read_any()
756 return intel_uncore_read(gt->uncore, mcr_reg_cast(reg)); in intel_gt_mcr_read_any()
760 struct intel_gt *gt, in report_steering_type() argument
769 if (!gt->steering_table[type]) { in report_steering_type()
775 get_nonterminated_steering(gt, type, &group, &instance); in report_steering_type()
782 for (entry = gt->steering_table[type]; entry->end; entry++) in report_steering_type()
786 void intel_gt_mcr_report_steering(struct drm_printer *p, struct intel_gt *gt, in intel_gt_mcr_report_steering() argument
793 if (GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)) in intel_gt_mcr_report_steering()
795 gt->default_steering.groupid, in intel_gt_mcr_report_steering()
796 gt->default_steering.instanceid); in intel_gt_mcr_report_steering()
798 if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)) { in intel_gt_mcr_report_steering()
800 if (gt->steering_table[i]) in intel_gt_mcr_report_steering()
801 report_steering_type(p, gt, i, dump_table); in intel_gt_mcr_report_steering()
802 } else if (IS_PONTEVECCHIO(gt->i915)) { in intel_gt_mcr_report_steering()
803 report_steering_type(p, gt, INSTANCE0, dump_table); in intel_gt_mcr_report_steering()
804 } else if (HAS_MSLICE_STEERING(gt->i915)) { in intel_gt_mcr_report_steering()
805 report_steering_type(p, gt, MSLICE, dump_table); in intel_gt_mcr_report_steering()
806 report_steering_type(p, gt, LNCF, dump_table); in intel_gt_mcr_report_steering()
812 * @gt: GT structure
820 void intel_gt_mcr_get_ss_steering(struct intel_gt *gt, unsigned int dss, in intel_gt_mcr_get_ss_steering() argument
823 if (IS_PONTEVECCHIO(gt->i915)) { in intel_gt_mcr_get_ss_steering()
826 } else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) { in intel_gt_mcr_get_ss_steering()
838 * @gt: GT structure
848 * (intel_gt_mcr_read_any_fw(gt, reg) & mask) == value
863 * Context: Calls a function that takes and releases gt->mcr_lock
866 int intel_gt_mcr_wait_for_reg(struct intel_gt *gt, in intel_gt_mcr_wait_for_reg() argument
875 lockdep_assert_not_held(>->mcr_lock); in intel_gt_mcr_wait_for_reg()
877 #define done ((intel_gt_mcr_read_any(gt, reg) & mask) == value) in intel_gt_mcr_wait_for_reg()