67 enum mipi_dsi_pixel_format pixel_format_from_register_bits(u32 fmt)  in pixel_format_from_register_bits()
90 	u32 mask;  in vlv_dsi_wait_for_fifo_empty()
102 		       const u8 *data, u32 len)  in write_data()
104 	u32 i, j;  in write_data()
107 		u32 val = 0;  in write_data()
109 		for (j = 0; j < min_t(u32, len - i, 4); j++)  in write_data()
118 		      u8 *data, u32 len)  in read_data()
120 	u32 i, j;  in read_data()
123 		u32 val = intel_de_read(dev_priv, reg);  in read_data()
125 		for (j = 0; j < min_t(u32, len - i, 4); j++)  in read_data()
141 	u32 data_mask, ctrl_mask;  in intel_dsi_host_transfer()
224 static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,  in dpi_send_cmd()
230 	u32 mask;  in dpi_send_cmd()
348 		u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port));  in glk_dsi_enable_io()
436 	u32 val;  in bxt_dsi_device_ready()
614 		u32 temp = intel_dsi->pixel_overlap;  in intel_dsi_port_enable()
631 		u32 temp;  in intel_dsi_port_enable()
972 			u32 tmp = intel_de_read(dev_priv,  in intel_dsi_get_hw_state()
984 			u32 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));  in intel_dsi_get_hw_state()
1174 	u32 pclk;  in intel_dsi_get_config()
1196 static u16 txclkesc(u32 divider, unsigned int us)  in txclkesc()
1281 static u32 pixel_format_to_reg(enum mipi_dsi_pixel_format fmt)  in pixel_format_to_reg()
1309 	u32 val, tmp;  in intel_dsi_prepare()
1477 			u32 fmt = intel_dsi->video_frmt_cfg_bits | IP_TG_CONFIG;  in intel_dsi_prepare()
1603 	u32 tlpx_ns, extra_byte_count, tlpx_ui;  in vlv_dphy_param_init()
1604 	u32 ui_num, ui_den;  in vlv_dphy_param_init()
1605 	u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;  in vlv_dphy_param_init()
1606 	u32 ths_prepare_ns, tclk_trail_ns;  in vlv_dphy_param_init()
1607 	u32 tclk_prepare_clkzero, ths_prepare_hszero;  in vlv_dphy_param_init()
1608 	u32 lp_to_hs_switch, hs_to_lp_switch;  in vlv_dphy_param_init()
1609 	u32 mul;  in vlv_dphy_param_init()