325 			    u32 val, bool psr2_enabled)  in psr_event_print()  argument
330 	if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled)  in psr_event_print()
358 	if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled)  in psr_event_print()
386 			psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled);  in intel_psr_irq_handler()
576 	if (intel_dp->psr.psr2_enabled) {  in intel_psr_enable_sink()
1292 	pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;  in intel_psr_get_config()
1295 	if (!intel_dp->psr.psr2_enabled)  in intel_psr_get_config()
1329 	if (intel_dp->psr.psr2_enabled)  in intel_psr_activate()
1453 	if (intel_dp->psr.psr2_enabled) {  in intel_psr_enable_source()
1519 	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;  in intel_psr_enable_locked()
1536 		    intel_dp->psr.psr2_enabled ? "2" : "1");  in intel_psr_enable_locked()
1565 	if (intel_dp->psr.psr2_enabled) {  in intel_psr_exit()
1588 	if (intel_dp->psr.psr2_enabled) {  in intel_psr_wait_exit_locked()
1615 		    intel_dp->psr.psr2_enabled ? "2" : "1");  in intel_psr_disable_locked()
1628 	if (intel_dp->psr.psr2_enabled) {  in intel_psr_disable_locked()
1644 	if (intel_dp->psr.psr2_enabled)  in intel_psr_disable_locked()
1648 	intel_dp->psr.psr2_enabled = false;  in intel_psr_disable_locked()
2197 		needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled;  in intel_psr_pre_plane_update()
2321 		if (intel_dp->psr.psr2_enabled)  in intel_psr_wait_for_idle_locked()
2342 	if (intel_dp->psr.psr2_enabled) {  in __psr_wait_for_idle_locked()
2583 	if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled ||  in tgl_dc3co_flush_locked()
2768 	if (!psr->psr2_enabled)  in psr_alpm_check()
2937 	if (intel_dp->psr.psr2_enabled) {  in psr_source_status()
2997 		status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled";  in intel_psr_status()
3009 	if (psr->psr2_enabled) {  in intel_psr_status()
3035 	if (psr->psr2_enabled) {  in intel_psr_status()