Lines Matching +full:charge +full:- +full:integration
4 * Permission is hereby granted, free of charge, to any person obtaining a
44 * Since Haswell Display controller supports Panel Self-Refresh on display
58 * The implementation uses the hardware-based PSR support which automatically
59 * enters/exits self-refresh mode. The hardware takes care of sending the
62 * changes to know when to exit self-refresh mode again. Unfortunately that
65 * update. For this integration intel_psr_invalidate() and intel_psr_flush()
67 * issues the self-refresh re-enable code is done from a work queue, which
75 * entry/exit allows the HW to enter a low-power state even when page flipping
91 * EDP_PSR_DEBUG[16]/EDP_PSR_DEBUG_MASK_DISP_REG_WRITE (hsw-skl):
155 * In standby mode (as opposed to link-off) this makes no difference
169 * The rest of the bits are more self-explanatory and/or
175 struct intel_connector *connector = intel_dp->attached_connector; in psr_global_enabled()
178 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr_global_enabled()
180 if (i915->params.enable_psr == -1) in psr_global_enabled()
181 return connector->panel.vbt.psr.enable; in psr_global_enabled()
182 return i915->params.enable_psr; in psr_global_enabled()
194 switch (intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK) { in psr2_global_enabled()
199 if (i915->params.enable_psr == 1) in psr2_global_enabled()
210 EDP_PSR_ERROR(intel_dp->psr.transcoder); in psr_irq_psr_error_bit_get()
218 EDP_PSR_POST_EXIT(intel_dp->psr.transcoder); in psr_irq_post_exit_bit_get()
226 EDP_PSR_PRE_ENTRY(intel_dp->psr.transcoder); in psr_irq_pre_entry_bit_get()
234 EDP_PSR_MASK(intel_dp->psr.transcoder); in psr_irq_mask_get()
312 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_irq_control()
316 if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) in psr_irq_control()
327 drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); in psr_event_print()
329 drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); in psr_event_print()
331 drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); in psr_event_print()
333 drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); in psr_event_print()
335 drm_dbg_kms(&i915->drm, "\tSU CRC FIFO underrun\n"); in psr_event_print()
337 drm_dbg_kms(&i915->drm, "\tGraphics reset\n"); in psr_event_print()
339 drm_dbg_kms(&i915->drm, "\tPCH interrupt\n"); in psr_event_print()
341 drm_dbg_kms(&i915->drm, "\tMemory up\n"); in psr_event_print()
343 drm_dbg_kms(&i915->drm, "\tFront buffer modification\n"); in psr_event_print()
345 drm_dbg_kms(&i915->drm, "\tPSR watchdog timer expired\n"); in psr_event_print()
347 drm_dbg_kms(&i915->drm, "\tPIPE registers updated\n"); in psr_event_print()
349 drm_dbg_kms(&i915->drm, "\tRegister updated\n"); in psr_event_print()
351 drm_dbg_kms(&i915->drm, "\tHDCP enabled\n"); in psr_event_print()
353 drm_dbg_kms(&i915->drm, "\tKVMR session enabled\n"); in psr_event_print()
355 drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); in psr_event_print()
357 drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); in psr_event_print()
359 drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); in psr_event_print()
365 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_irq_handler()
369 intel_dp->psr.last_entry_attempt = time_ns; in intel_psr_irq_handler()
370 drm_dbg_kms(&dev_priv->drm, in intel_psr_irq_handler()
376 intel_dp->psr.last_exit = time_ns; in intel_psr_irq_handler()
377 drm_dbg_kms(&dev_priv->drm, in intel_psr_irq_handler()
386 psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled); in intel_psr_irq_handler()
391 drm_warn(&dev_priv->drm, "[transcoder %s] PSR aux error\n", in intel_psr_irq_handler()
394 intel_dp->psr.irq_aux_error = true; in intel_psr_irq_handler()
407 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in intel_psr_irq_handler()
415 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, in intel_dp_get_alpm_status()
426 if (drm_dp_dpcd_readb(&intel_dp->aux, in intel_dp_get_sink_sync_latency()
430 drm_dbg_kms(&i915->drm, in intel_dp_get_sink_sync_latency()
443 if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { in intel_dp_get_su_granularity()
450 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); in intel_dp_get_su_granularity()
452 drm_dbg_kms(&i915->drm, in intel_dp_get_su_granularity()
461 r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); in intel_dp_get_su_granularity()
463 drm_dbg_kms(&i915->drm, in intel_dp_get_su_granularity()
471 intel_dp->psr.su_w_granularity = w; in intel_dp_get_su_granularity()
472 intel_dp->psr.su_y_granularity = y; in intel_dp_get_su_granularity()
478 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); in intel_psr_init_dpcd()
480 drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, in intel_psr_init_dpcd()
481 sizeof(intel_dp->psr_dpcd)); in intel_psr_init_dpcd()
483 if (!intel_dp->psr_dpcd[0]) in intel_psr_init_dpcd()
485 drm_dbg_kms(&dev_priv->drm, "eDP panel supports PSR version %x\n", in intel_psr_init_dpcd()
486 intel_dp->psr_dpcd[0]); in intel_psr_init_dpcd()
488 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_PSR)) { in intel_psr_init_dpcd()
489 drm_dbg_kms(&dev_priv->drm, in intel_psr_init_dpcd()
494 if (!(intel_dp->edp_dpcd[1] & DP_EDP_SET_POWER_CAP)) { in intel_psr_init_dpcd()
495 drm_dbg_kms(&dev_priv->drm, in intel_psr_init_dpcd()
500 intel_dp->psr.sink_support = true; in intel_psr_init_dpcd()
501 intel_dp->psr.sink_sync_latency = in intel_psr_init_dpcd()
505 (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_IS_SUPPORTED)) { in intel_psr_init_dpcd()
506 bool y_req = intel_dp->psr_dpcd[1] & in intel_psr_init_dpcd()
512 * Y-coordinate) can handle Y-coordinates in VSC but we are in intel_psr_init_dpcd()
518 * Y-coordinate requirement panels we would need to enable in intel_psr_init_dpcd()
521 intel_dp->psr.sink_psr2_support = y_req && alpm; in intel_psr_init_dpcd()
522 drm_dbg_kms(&dev_priv->drm, "PSR2 %ssupported\n", in intel_psr_init_dpcd()
523 intel_dp->psr.sink_psr2_support ? "" : "not "); in intel_psr_init_dpcd()
525 if (intel_dp->psr.sink_psr2_support) { in intel_psr_init_dpcd()
526 intel_dp->psr.colorimetry_support = in intel_psr_init_dpcd()
536 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_psr_setup_aux()
543 [3] = 1 - 1, in hsw_psr_setup_aux()
552 intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); in hsw_psr_setup_aux()
554 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); in hsw_psr_setup_aux()
557 aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), in hsw_psr_setup_aux()
576 if (intel_dp->psr.psr2_enabled) { in intel_psr_enable_sink()
577 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, in intel_psr_enable_sink()
583 if (intel_dp->psr.link_standby) in intel_psr_enable_sink()
590 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in intel_psr_enable_sink()
593 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); in intel_psr_enable_sink()
595 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_enable_sink()
600 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr1_get_tp_time()
607 if (dev_priv->params.psr_safest_params) { in intel_psr1_get_tp_time()
613 if (connector->panel.vbt.psr.tp1_wakeup_time_us == 0) in intel_psr1_get_tp_time()
615 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
617 else if (connector->panel.vbt.psr.tp1_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
622 if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
624 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 100) in intel_psr1_get_tp_time()
626 else if (connector->panel.vbt.psr.tp2_tp3_wakeup_time_us <= 500) in intel_psr1_get_tp_time()
636 connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && in intel_psr1_get_tp_time()
637 connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) in intel_psr1_get_tp_time()
642 drm_dp_tps3_supported(intel_dp->dpcd)) in intel_psr1_get_tp_time()
652 struct intel_connector *connector = intel_dp->attached_connector; in psr_compute_idle_frames()
657 * off-by-one issue that HW has in some cases. in psr_compute_idle_frames()
659 idle_frames = max(6, connector->panel.vbt.psr.idle_frames); in psr_compute_idle_frames()
660 idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1); in psr_compute_idle_frames()
662 if (drm_WARN_ON(&dev_priv->drm, idle_frames > 0xf)) in psr_compute_idle_frames()
671 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr1()
683 if (intel_dp->psr.link_standby) in hsw_activate_psr1()
697 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr2_get_tp_time()
701 if (dev_priv->params.psr_safest_params) in intel_psr2_get_tp_time()
704 if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us >= 0 && in intel_psr2_get_tp_time()
705 connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 50) in intel_psr2_get_tp_time()
707 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 100) in intel_psr2_get_tp_time()
709 else if (connector->panel.vbt.psr.psr2_tp2_tp3_wakeup_time_us <= 500) in intel_psr2_get_tp_time()
719 return intel_dp->psr.io_wake_lines < 9 && in psr2_block_count_lines()
720 intel_dp->psr.fast_wake_lines < 9 ? 8 : 12; in psr2_block_count_lines()
731 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in hsw_activate_psr2()
742 val |= EDP_PSR2_FRAME_BEFORE_SU(max_t(u8, intel_dp->psr.sink_sync_latency + 1, 2)); in hsw_activate_psr2()
752 /* Wa_22012278275:adl-p */ in hsw_activate_psr2()
770 tmp = map[intel_dp->psr.io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; in hsw_activate_psr2()
773 tmp = map[intel_dp->psr.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; in hsw_activate_psr2()
776 val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); in hsw_activate_psr2()
777 val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); in hsw_activate_psr2()
779 val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->psr.io_wake_lines); in hsw_activate_psr2()
780 val |= EDP_PSR2_FAST_WAKE(intel_dp->psr.fast_wake_lines); in hsw_activate_psr2()
783 if (intel_dp->psr.req_psr2_sdp_prior_scanline) in hsw_activate_psr2()
786 if (intel_dp->psr.psr2_sel_fetch_enabled) { in hsw_activate_psr2()
790 drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); in hsw_activate_psr2()
819 if (!cstate || !cstate->hw.active) in intel_get_frame_time_us()
823 drm_mode_vrefresh(&cstate->hw.adjusted_mode)); in intel_get_frame_time_us()
830 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr2_program_idle_frames()
858 mutex_lock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
860 if (delayed_work_pending(&intel_dp->psr.dc3co_work)) in tgl_dc3co_disable_work()
865 mutex_unlock(&intel_dp->psr.lock); in tgl_dc3co_disable_work()
870 if (!intel_dp->psr.dc3co_exitline) in tgl_disallow_dc3co_on_psr2_exit()
873 cancel_delayed_work(&intel_dp->psr.dc3co_work); in tgl_disallow_dc3co_on_psr2_exit()
883 enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in dc3co_is_pipe_port_compatible()
885 enum port port = dig_port->base.port; in dc3co_is_pipe_port_compatible()
897 const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay; in tgl_dc3co_exitline_compute_config()
899 struct i915_power_domains *power_domains = &dev_priv->display.power.domains; in tgl_dc3co_exitline_compute_config()
913 if (crtc_state->enable_psr2_sel_fetch) in tgl_dc3co_exitline_compute_config()
916 if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO)) in tgl_dc3co_exitline_compute_config()
922 /* Wa_16011303918:adl-p */ in tgl_dc3co_exitline_compute_config()
931 intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1; in tgl_dc3co_exitline_compute_config()
933 if (drm_WARN_ON(&dev_priv->drm, exit_scanlines > crtc_vdisplay)) in tgl_dc3co_exitline_compute_config()
936 crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines; in tgl_dc3co_exitline_compute_config()
944 if (!dev_priv->params.enable_psr2_sel_fetch && in intel_psr2_sel_fetch_config_valid()
945 intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) { in intel_psr2_sel_fetch_config_valid()
946 drm_dbg_kms(&dev_priv->drm, in intel_psr2_sel_fetch_config_valid()
951 if (crtc_state->uapi.async_flip) { in intel_psr2_sel_fetch_config_valid()
952 drm_dbg_kms(&dev_priv->drm, in intel_psr2_sel_fetch_config_valid()
957 return crtc_state->enable_psr2_sel_fetch = true; in intel_psr2_sel_fetch_config_valid()
964 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in psr2_granularity_check()
965 const int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in psr2_granularity_check()
966 const int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in psr2_granularity_check()
970 if (crtc_hdisplay % intel_dp->psr.su_w_granularity) in psr2_granularity_check()
973 if (crtc_vdisplay % intel_dp->psr.su_y_granularity) in psr2_granularity_check()
977 if (!crtc_state->enable_psr2_sel_fetch) in psr2_granularity_check()
978 return intel_dp->psr.su_y_granularity == 4; in psr2_granularity_check()
986 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
987 else if (intel_dp->psr.su_y_granularity <= 2) in psr2_granularity_check()
989 else if ((intel_dp->psr.su_y_granularity % 4) == 0) in psr2_granularity_check()
990 y_granularity = intel_dp->psr.su_y_granularity; in psr2_granularity_check()
995 if (crtc_state->dsc.compression_enable && in psr2_granularity_check()
996 vdsc_cfg->slice_height % y_granularity) in psr2_granularity_check()
999 crtc_state->su_y_granularity = y_granularity; in psr2_granularity_check()
1006 const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode; in _compute_psr2_sdp_prior_scanline_indication()
1010 hblank_total = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; in _compute_psr2_sdp_prior_scanline_indication()
1011 hblank_ns = div_u64(1000000ULL * hblank_total, adjusted_mode->crtc_clock); in _compute_psr2_sdp_prior_scanline_indication()
1014 req_ns = ((60 / crtc_state->lane_count) + 11) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
1016 if ((hblank_ns - req_ns) > 100) in _compute_psr2_sdp_prior_scanline_indication()
1019 /* Not supported <13 / Wa_22012279113:adl-p */ in _compute_psr2_sdp_prior_scanline_indication()
1020 if (DISPLAY_VER(dev_priv) <= 13 || intel_dp->edp_dpcd[0] < DP_EDP_14b) in _compute_psr2_sdp_prior_scanline_indication()
1023 crtc_state->req_psr2_sdp_prior_scanline = true; in _compute_psr2_sdp_prior_scanline_indication()
1038 * it is not enough -> use 45 us. in _compute_psr2_wake_times()
1049 &crtc_state->hw.adjusted_mode, io_wake_time); in _compute_psr2_wake_times()
1051 &crtc_state->hw.adjusted_mode, fast_wake_time); in _compute_psr2_wake_times()
1057 if (i915->params.psr_safest_params) in _compute_psr2_wake_times()
1061 intel_dp->psr.io_wake_lines = max(io_wake_lines, 7); in _compute_psr2_wake_times()
1062 intel_dp->psr.fast_wake_lines = max(fast_wake_lines, 7); in _compute_psr2_wake_times()
1071 int crtc_hdisplay = crtc_state->hw.adjusted_mode.crtc_hdisplay; in intel_psr2_config_valid()
1072 int crtc_vdisplay = crtc_state->hw.adjusted_mode.crtc_vdisplay; in intel_psr2_config_valid()
1075 if (!intel_dp->psr.sink_psr2_support) in intel_psr2_config_valid()
1080 drm_dbg_kms(&dev_priv->drm, "PSR2 not supported by phy\n"); in intel_psr2_config_valid()
1087 drm_dbg_kms(&dev_priv->drm, "PSR2 is defeatured for this platform\n"); in intel_psr2_config_valid()
1092 drm_dbg_kms(&dev_priv->drm, "PSR2 not completely functional in this stepping\n"); in intel_psr2_config_valid()
1096 if (!transcoder_has_psr2(dev_priv, crtc_state->cpu_transcoder)) { in intel_psr2_config_valid()
1097 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1099 transcoder_name(crtc_state->cpu_transcoder)); in intel_psr2_config_valid()
1104 drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); in intel_psr2_config_valid()
1113 if (crtc_state->dsc.compression_enable && in intel_psr2_config_valid()
1115 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1120 if (crtc_state->crc_enabled) { in intel_psr2_config_valid()
1121 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1140 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
1141 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1143 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
1147 /* Wa_16011303918:adl-p */ in intel_psr2_config_valid()
1148 if (crtc_state->vrr.enable && in intel_psr2_config_valid()
1150 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1156 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1162 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1168 if (crtc_state->hw.adjusted_mode.crtc_vblank_end - in intel_psr2_config_valid()
1169 crtc_state->hw.adjusted_mode.crtc_vblank_start < in intel_psr2_config_valid()
1171 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1179 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1186 drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); in intel_psr2_config_valid()
1190 if (!crtc_state->enable_psr2_sel_fetch && in intel_psr2_config_valid()
1192 drm_dbg_kms(&dev_priv->drm, in intel_psr2_config_valid()
1203 crtc_state->enable_psr2_sel_fetch = false; in intel_psr2_config_valid()
1213 &crtc_state->hw.adjusted_mode; in intel_psr_compute_config()
1220 if (crtc_state->vrr.enable) in intel_psr_compute_config()
1227 drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); in intel_psr_compute_config()
1231 if (intel_dp->psr.sink_not_reliable) { in intel_psr_compute_config()
1232 drm_dbg_kms(&dev_priv->drm, in intel_psr_compute_config()
1237 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { in intel_psr_compute_config()
1238 drm_dbg_kms(&dev_priv->drm, in intel_psr_compute_config()
1243 psr_setup_time = drm_dp_psr_setup_time(intel_dp->psr_dpcd); in intel_psr_compute_config()
1245 drm_dbg_kms(&dev_priv->drm, in intel_psr_compute_config()
1247 intel_dp->psr_dpcd[1]); in intel_psr_compute_config()
1252 adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vdisplay - 1) { in intel_psr_compute_config()
1253 drm_dbg_kms(&dev_priv->drm, in intel_psr_compute_config()
1259 crtc_state->has_psr = true; in intel_psr_compute_config()
1260 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); in intel_psr_compute_config()
1262 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_psr_compute_config()
1264 &crtc_state->psr_vsc); in intel_psr_compute_config()
1270 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_psr_get_config()
1272 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_psr_get_config()
1279 intel_dp = &dig_port->dp; in intel_psr_get_config()
1283 mutex_lock(&intel_dp->psr.lock); in intel_psr_get_config()
1284 if (!intel_dp->psr.enabled) in intel_psr_get_config()
1291 pipe_config->has_psr = true; in intel_psr_get_config()
1292 pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; in intel_psr_get_config()
1293 pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); in intel_psr_get_config()
1295 if (!intel_dp->psr.psr2_enabled) in intel_psr_get_config()
1301 pipe_config->enable_psr2_sel_fetch = true; in intel_psr_get_config()
1306 pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); in intel_psr_get_config()
1309 mutex_unlock(&intel_dp->psr.lock); in intel_psr_get_config()
1315 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_activate()
1317 drm_WARN_ON(&dev_priv->drm, in intel_psr_activate()
1321 drm_WARN_ON(&dev_priv->drm, in intel_psr_activate()
1324 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); in intel_psr_activate()
1326 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_activate()
1329 if (intel_dp->psr.psr2_enabled) in intel_psr_activate()
1334 intel_dp->psr.active = true; in intel_psr_activate()
1339 switch (intel_dp->psr.pipe) { in wa_16013835468_bit_get()
1349 MISSING_CASE(intel_dp->psr.pipe); in wa_16013835468_bit_get()
1367 set_wa_bit |= crtc_state->wm_level_disabled; in wm_optimization_wa()
1371 set_wa_bit |= crtc_state->hw.adjusted_mode.crtc_vblank_start != in wm_optimization_wa()
1372 crtc_state->hw.adjusted_mode.crtc_vdisplay; in wm_optimization_wa()
1386 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_enable_source()
1406 * For some unknown reason on HSW non-ULT (or at least on in intel_psr_enable_source()
1438 if (intel_dp->psr.dc3co_exitline) in intel_psr_enable_source()
1440 intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); in intel_psr_enable_source()
1444 intel_dp->psr.psr2_sel_fetch_enabled ? in intel_psr_enable_source()
1453 if (intel_dp->psr.psr2_enabled) { in intel_psr_enable_source()
1461 * All supported adlp panels have 1-based X granularity, this may in intel_psr_enable_source()
1462 * cause issues if non-supported panels are used. in intel_psr_enable_source()
1485 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_interrupt_error_check()
1499 intel_dp->psr.sink_not_reliable = true; in psr_interrupt_error_check()
1500 drm_dbg_kms(&dev_priv->drm, in psr_interrupt_error_check()
1513 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); in intel_psr_enable_locked()
1514 struct intel_encoder *encoder = &dig_port->base; in intel_psr_enable_locked()
1517 drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); in intel_psr_enable_locked()
1519 intel_dp->psr.psr2_enabled = crtc_state->has_psr2; in intel_psr_enable_locked()
1520 intel_dp->psr.busy_frontbuffer_bits = 0; in intel_psr_enable_locked()
1521 intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; in intel_psr_enable_locked()
1522 intel_dp->psr.transcoder = crtc_state->cpu_transcoder; in intel_psr_enable_locked()
1525 intel_dp->psr.dc3co_exit_delay = val; in intel_psr_enable_locked()
1526 intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; in intel_psr_enable_locked()
1527 intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; in intel_psr_enable_locked()
1528 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_enable_locked()
1529 intel_dp->psr.req_psr2_sdp_prior_scanline = in intel_psr_enable_locked()
1530 crtc_state->req_psr2_sdp_prior_scanline; in intel_psr_enable_locked()
1535 drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", in intel_psr_enable_locked()
1536 intel_dp->psr.psr2_enabled ? "2" : "1"); in intel_psr_enable_locked()
1537 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); in intel_psr_enable_locked()
1541 intel_dp->psr.enabled = true; in intel_psr_enable_locked()
1542 intel_dp->psr.paused = false; in intel_psr_enable_locked()
1550 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_exit()
1553 if (!intel_dp->psr.active) { in intel_psr_exit()
1556 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); in intel_psr_exit()
1560 drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); in intel_psr_exit()
1565 if (intel_dp->psr.psr2_enabled) { in intel_psr_exit()
1571 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); in intel_psr_exit()
1576 drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); in intel_psr_exit()
1578 intel_dp->psr.active = false; in intel_psr_exit()
1584 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_wait_exit_locked()
1588 if (intel_dp->psr.psr2_enabled) { in intel_psr_wait_exit_locked()
1599 drm_err(&dev_priv->drm, "Timed out waiting PSR idle state\n"); in intel_psr_wait_exit_locked()
1605 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_disable_locked()
1607 dp_to_dig_port(intel_dp)->base.port); in intel_psr_disable_locked()
1609 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_disable_locked()
1611 if (!intel_dp->psr.enabled) in intel_psr_disable_locked()
1614 drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", in intel_psr_disable_locked()
1615 intel_dp->psr.psr2_enabled ? "2" : "1"); in intel_psr_disable_locked()
1628 if (intel_dp->psr.psr2_enabled) { in intel_psr_disable_locked()
1642 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); in intel_psr_disable_locked()
1644 if (intel_dp->psr.psr2_enabled) in intel_psr_disable_locked()
1645 drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); in intel_psr_disable_locked()
1647 intel_dp->psr.enabled = false; in intel_psr_disable_locked()
1648 intel_dp->psr.psr2_enabled = false; in intel_psr_disable_locked()
1649 intel_dp->psr.psr2_sel_fetch_enabled = false; in intel_psr_disable_locked()
1650 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in intel_psr_disable_locked()
1654 * intel_psr_disable - Disable PSR
1665 if (!old_crtc_state->has_psr) in intel_psr_disable()
1668 if (drm_WARN_ON(&dev_priv->drm, !CAN_PSR(intel_dp))) in intel_psr_disable()
1671 mutex_lock(&intel_dp->psr.lock); in intel_psr_disable()
1675 mutex_unlock(&intel_dp->psr.lock); in intel_psr_disable()
1676 cancel_work_sync(&intel_dp->psr.work); in intel_psr_disable()
1677 cancel_delayed_work_sync(&intel_dp->psr.dc3co_work); in intel_psr_disable()
1681 * intel_psr_pause - Pause PSR
1689 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pause()
1694 mutex_lock(&psr->lock); in intel_psr_pause()
1696 if (!psr->enabled) { in intel_psr_pause()
1697 mutex_unlock(&psr->lock); in intel_psr_pause()
1702 drm_WARN_ON(&dev_priv->drm, psr->paused); in intel_psr_pause()
1706 psr->paused = true; in intel_psr_pause()
1708 mutex_unlock(&psr->lock); in intel_psr_pause()
1710 cancel_work_sync(&psr->work); in intel_psr_pause()
1711 cancel_delayed_work_sync(&psr->dc3co_work); in intel_psr_pause()
1715 * intel_psr_resume - Resume PSR
1722 struct intel_psr *psr = &intel_dp->psr; in intel_psr_resume()
1727 mutex_lock(&psr->lock); in intel_psr_resume()
1729 if (!psr->paused) in intel_psr_resume()
1732 psr->paused = false; in intel_psr_resume()
1736 mutex_unlock(&psr->lock); in intel_psr_resume()
1769 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_force_hw_tracking_exit()
1771 if (intel_dp->psr.psr2_sel_fetch_enabled) in psr_force_hw_tracking_exit()
1783 * instead of disabling and re-enabling. in psr_force_hw_tracking_exit()
1792 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in psr_force_hw_tracking_exit()
1798 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_psr2_disable_plane_sel_fetch_arm()
1799 enum pipe pipe = plane->pipe; in intel_psr2_disable_plane_sel_fetch_arm()
1801 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_disable_plane_sel_fetch_arm()
1804 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); in intel_psr2_disable_plane_sel_fetch_arm()
1811 struct drm_i915_private *i915 = to_i915(plane->base.dev); in intel_psr2_program_plane_sel_fetch_arm()
1812 enum pipe pipe = plane->pipe; in intel_psr2_program_plane_sel_fetch_arm()
1814 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_plane_sel_fetch_arm()
1817 if (plane->id == PLANE_CURSOR) in intel_psr2_program_plane_sel_fetch_arm()
1818 intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), in intel_psr2_program_plane_sel_fetch_arm()
1819 plane_state->ctl); in intel_psr2_program_plane_sel_fetch_arm()
1821 intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), in intel_psr2_program_plane_sel_fetch_arm()
1830 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_psr2_program_plane_sel_fetch_noarm()
1831 enum pipe pipe = plane->pipe; in intel_psr2_program_plane_sel_fetch_noarm()
1836 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_plane_sel_fetch_noarm()
1839 if (plane->id == PLANE_CURSOR) in intel_psr2_program_plane_sel_fetch_noarm()
1842 clip = &plane_state->psr2_sel_fetch_area; in intel_psr2_program_plane_sel_fetch_noarm()
1844 val = (clip->y1 + plane_state->uapi.dst.y1) << 16; in intel_psr2_program_plane_sel_fetch_noarm()
1845 val |= plane_state->uapi.dst.x1; in intel_psr2_program_plane_sel_fetch_noarm()
1846 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); in intel_psr2_program_plane_sel_fetch_noarm()
1848 x = plane_state->view.color_plane[color_plane].x; in intel_psr2_program_plane_sel_fetch_noarm()
1855 y = plane_state->view.color_plane[color_plane].y + clip->y1; in intel_psr2_program_plane_sel_fetch_noarm()
1857 y = plane_state->view.color_plane[color_plane].y + clip->y1 / 2; in intel_psr2_program_plane_sel_fetch_noarm()
1861 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), in intel_psr2_program_plane_sel_fetch_noarm()
1865 val = (drm_rect_height(clip) - 1) << 16; in intel_psr2_program_plane_sel_fetch_noarm()
1866 val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; in intel_psr2_program_plane_sel_fetch_noarm()
1867 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); in intel_psr2_program_plane_sel_fetch_noarm()
1872 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_program_trans_man_trk_ctl()
1873 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_psr2_program_trans_man_trk_ctl()
1876 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_program_trans_man_trk_ctl()
1879 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, in intel_psr2_program_trans_man_trk_ctl()
1880 crtc_state->uapi.encoder_mask) { in intel_psr2_program_trans_man_trk_ctl()
1883 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr2_program_trans_man_trk_ctl()
1884 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) in intel_psr2_program_trans_man_trk_ctl()
1890 crtc_state->psr2_man_track_ctl); in intel_psr2_program_trans_man_trk_ctl()
1896 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in psr2_man_trk_ctl_calc()
1897 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in psr2_man_trk_ctl_calc()
1909 if (clip->y1 == -1) in psr2_man_trk_ctl_calc()
1913 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1); in psr2_man_trk_ctl_calc()
1914 val |= ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 - 1); in psr2_man_trk_ctl_calc()
1916 drm_WARN_ON(crtc_state->uapi.crtc->dev, clip->y1 % 4 || clip->y2 % 4); in psr2_man_trk_ctl_calc()
1918 val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); in psr2_man_trk_ctl_calc()
1919 val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(clip->y2 / 4 + 1); in psr2_man_trk_ctl_calc()
1922 crtc_state->psr2_man_track_ctl = val; in psr2_man_trk_ctl_calc()
1932 if (overlap_damage_area->y1 == -1) { in clip_area_update()
1933 overlap_damage_area->y1 = damage_area->y1; in clip_area_update()
1934 overlap_damage_area->y2 = damage_area->y2; in clip_area_update()
1938 if (damage_area->y1 < overlap_damage_area->y1) in clip_area_update()
1939 overlap_damage_area->y1 = damage_area->y1; in clip_area_update()
1941 if (damage_area->y2 > overlap_damage_area->y2) in clip_area_update()
1942 overlap_damage_area->y2 = damage_area->y2; in clip_area_update()
1948 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_psr2_sel_fetch_pipe_alignment()
1949 const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in intel_psr2_sel_fetch_pipe_alignment()
1953 if (crtc_state->dsc.compression_enable && in intel_psr2_sel_fetch_pipe_alignment()
1955 y_alignment = vdsc_cfg->slice_height; in intel_psr2_sel_fetch_pipe_alignment()
1957 y_alignment = crtc_state->su_y_granularity; in intel_psr2_sel_fetch_pipe_alignment()
1959 pipe_clip->y1 -= pipe_clip->y1 % y_alignment; in intel_psr2_sel_fetch_pipe_alignment()
1960 if (pipe_clip->y2 % y_alignment) in intel_psr2_sel_fetch_pipe_alignment()
1961 pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1) * y_alignment; in intel_psr2_sel_fetch_pipe_alignment()
1975 if (plane_state->uapi.dst.y1 < 0 || in psr2_sel_fetch_plane_state_supported()
1976 plane_state->uapi.dst.x1 < 0 || in psr2_sel_fetch_plane_state_supported()
1977 plane_state->scaler_id >= 0 || in psr2_sel_fetch_plane_state_supported()
1978 plane_state->uapi.rotation != DRM_MODE_ROTATE_0) in psr2_sel_fetch_plane_state_supported()
1993 if (crtc_state->scaler_state.scaler_id >= 0) in psr2_sel_fetch_pipe_state_supported()
2002 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_psr2_sel_fetch_update()
2004 struct drm_rect pipe_clip = { .x1 = 0, .y1 = -1, .x2 = INT_MAX, .y2 = -1 }; in intel_psr2_sel_fetch_update()
2010 if (!crtc_state->enable_psr2_sel_fetch) in intel_psr2_sel_fetch_update()
2026 struct drm_rect src, damaged_area = { .x1 = 0, .y1 = -1, in intel_psr2_sel_fetch_update()
2029 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) in intel_psr2_sel_fetch_update()
2032 if (!new_plane_state->uapi.visible && in intel_psr2_sel_fetch_update()
2033 !old_plane_state->uapi.visible) in intel_psr2_sel_fetch_update()
2046 if (new_plane_state->uapi.visible != old_plane_state->uapi.visible || in intel_psr2_sel_fetch_update()
2047 !drm_rect_equals(&new_plane_state->uapi.dst, in intel_psr2_sel_fetch_update()
2048 &old_plane_state->uapi.dst)) { in intel_psr2_sel_fetch_update()
2049 if (old_plane_state->uapi.visible) { in intel_psr2_sel_fetch_update()
2050 damaged_area.y1 = old_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2051 damaged_area.y2 = old_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2053 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2056 if (new_plane_state->uapi.visible) { in intel_psr2_sel_fetch_update()
2057 damaged_area.y1 = new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2058 damaged_area.y2 = new_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2060 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2063 } else if (new_plane_state->uapi.alpha != old_plane_state->uapi.alpha) { in intel_psr2_sel_fetch_update()
2065 damaged_area.y1 = new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2066 damaged_area.y2 = new_plane_state->uapi.dst.y2; in intel_psr2_sel_fetch_update()
2068 &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2072 src = drm_plane_state_src(&new_plane_state->uapi); in intel_psr2_sel_fetch_update()
2075 if (!drm_atomic_helper_damage_merged(&old_plane_state->uapi, in intel_psr2_sel_fetch_update()
2076 &new_plane_state->uapi, &damaged_area)) in intel_psr2_sel_fetch_update()
2079 damaged_area.y1 += new_plane_state->uapi.dst.y1 - src.y1; in intel_psr2_sel_fetch_update()
2080 damaged_area.y2 += new_plane_state->uapi.dst.y1 - src.y1; in intel_psr2_sel_fetch_update()
2081 damaged_area.x1 += new_plane_state->uapi.dst.x1 - src.x1; in intel_psr2_sel_fetch_update()
2082 damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1; in intel_psr2_sel_fetch_update()
2084 clip_area_update(&pipe_clip, &damaged_area, &crtc_state->pipe_src); in intel_psr2_sel_fetch_update()
2093 if (pipe_clip.y1 == -1) { in intel_psr2_sel_fetch_update()
2094 drm_info_once(&dev_priv->drm, in intel_psr2_sel_fetch_update()
2096 pipe_name(crtc->pipe)); in intel_psr2_sel_fetch_update()
2106 crtc_state->splitter.enable) in intel_psr2_sel_fetch_update()
2109 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); in intel_psr2_sel_fetch_update()
2122 struct intel_plane *linked = new_plane_state->planar_linked_plane; in intel_psr2_sel_fetch_update()
2124 if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc || in intel_psr2_sel_fetch_update()
2125 !new_plane_state->uapi.visible) in intel_psr2_sel_fetch_update()
2129 if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst)) in intel_psr2_sel_fetch_update()
2137 sel_fetch_area = &new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2138 sel_fetch_area->y1 = inter.y1 - new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2139 sel_fetch_area->y2 = inter.y2 - new_plane_state->uapi.dst.y1; in intel_psr2_sel_fetch_update()
2140 crtc_state->update_planes |= BIT(plane->id); in intel_psr2_sel_fetch_update()
2154 linked_sel_fetch_area = &linked_new_plane_state->psr2_sel_fetch_area; in intel_psr2_sel_fetch_update()
2155 linked_sel_fetch_area->y1 = sel_fetch_area->y1; in intel_psr2_sel_fetch_update()
2156 linked_sel_fetch_area->y2 = sel_fetch_area->y2; in intel_psr2_sel_fetch_update()
2157 crtc_state->update_planes |= BIT(linked->id); in intel_psr2_sel_fetch_update()
2169 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_psr_pre_plane_update()
2179 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, in intel_psr_pre_plane_update()
2180 old_crtc_state->uapi.encoder_mask) { in intel_psr_pre_plane_update()
2182 struct intel_psr *psr = &intel_dp->psr; in intel_psr_pre_plane_update()
2185 mutex_lock(&psr->lock); in intel_psr_pre_plane_update()
2189 * - PSR disabled in new state in intel_psr_pre_plane_update()
2190 * - All planes will go inactive in intel_psr_pre_plane_update()
2191 * - Changing between PSR versions in intel_psr_pre_plane_update()
2192 * - Display WA #1136: skl, bxt in intel_psr_pre_plane_update()
2195 needs_to_disable |= !new_crtc_state->has_psr; in intel_psr_pre_plane_update()
2196 needs_to_disable |= !new_crtc_state->active_planes; in intel_psr_pre_plane_update()
2197 needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; in intel_psr_pre_plane_update()
2199 new_crtc_state->wm_level_disabled; in intel_psr_pre_plane_update()
2201 if (psr->enabled && needs_to_disable) in intel_psr_pre_plane_update()
2203 else if (psr->enabled && new_crtc_state->wm_level_disabled) in intel_psr_pre_plane_update()
2207 mutex_unlock(&psr->lock); in intel_psr_pre_plane_update()
2214 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in _intel_psr_post_plane_update()
2217 if (!crtc_state->has_psr) in _intel_psr_post_plane_update()
2220 for_each_intel_encoder_mask_with_psr(state->base.dev, encoder, in _intel_psr_post_plane_update()
2221 crtc_state->uapi.encoder_mask) { in _intel_psr_post_plane_update()
2223 struct intel_psr *psr = &intel_dp->psr; in _intel_psr_post_plane_update()
2226 mutex_lock(&psr->lock); in _intel_psr_post_plane_update()
2228 drm_WARN_ON(&dev_priv->drm, psr->enabled && !crtc_state->active_planes); in _intel_psr_post_plane_update()
2230 keep_disabled |= psr->sink_not_reliable; in _intel_psr_post_plane_update()
2231 keep_disabled |= !crtc_state->active_planes; in _intel_psr_post_plane_update()
2235 crtc_state->wm_level_disabled; in _intel_psr_post_plane_update()
2237 if (!psr->enabled && !keep_disabled) in _intel_psr_post_plane_update()
2239 else if (psr->enabled && !crtc_state->wm_level_disabled) in _intel_psr_post_plane_update()
2244 if (crtc_state->crc_enabled && psr->enabled) in _intel_psr_post_plane_update()
2247 mutex_unlock(&psr->lock); in _intel_psr_post_plane_update()
2253 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_psr_post_plane_update()
2268 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr2_ready_for_pipe_update_locked()
2283 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr1_ready_for_pipe_update_locked()
2297 * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update
2305 struct drm_i915_private *dev_priv = to_i915(new_crtc_state->uapi.crtc->dev); in intel_psr_wait_for_idle_locked()
2308 if (!new_crtc_state->has_psr) in intel_psr_wait_for_idle_locked()
2311 for_each_intel_encoder_mask_with_psr(&dev_priv->drm, encoder, in intel_psr_wait_for_idle_locked()
2312 new_crtc_state->uapi.encoder_mask) { in intel_psr_wait_for_idle_locked()
2316 lockdep_assert_held(&intel_dp->psr.lock); in intel_psr_wait_for_idle_locked()
2318 if (!intel_dp->psr.enabled) in intel_psr_wait_for_idle_locked()
2321 if (intel_dp->psr.psr2_enabled) in intel_psr_wait_for_idle_locked()
2327 drm_err(&dev_priv->drm, "PSR wait timed out, atomic update may fail\n"); in intel_psr_wait_for_idle_locked()
2334 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in __psr_wait_for_idle_locked()
2339 if (!intel_dp->psr.enabled) in __psr_wait_for_idle_locked()
2342 if (intel_dp->psr.psr2_enabled) { in __psr_wait_for_idle_locked()
2350 mutex_unlock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2354 drm_err(&dev_priv->drm, in __psr_wait_for_idle_locked()
2355 "Timed out waiting for PSR Idle for re-enable\n"); in __psr_wait_for_idle_locked()
2358 mutex_lock(&intel_dp->psr.lock); in __psr_wait_for_idle_locked()
2359 return err == 0 && intel_dp->psr.enabled; in __psr_wait_for_idle_locked()
2370 state = drm_atomic_state_alloc(&dev_priv->drm); in intel_psr_fastset_force()
2372 return -ENOMEM; in intel_psr_fastset_force()
2376 state->acquire_ctx = &ctx; in intel_psr_fastset_force()
2377 to_intel_atomic_state(state)->internal = true; in intel_psr_fastset_force()
2380 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); in intel_psr_fastset_force()
2385 if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) in intel_psr_fastset_force()
2394 if (!conn_state->crtc) in intel_psr_fastset_force()
2397 crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); in intel_psr_fastset_force()
2403 /* Mark mode as changed to trigger a pipe->update() */ in intel_psr_fastset_force()
2404 crtc_state->mode_changed = true; in intel_psr_fastset_force()
2411 if (err == -EDEADLK) { in intel_psr_fastset_force()
2434 drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); in intel_psr_debug_set()
2435 return -EINVAL; in intel_psr_debug_set()
2438 ret = mutex_lock_interruptible(&intel_dp->psr.lock); in intel_psr_debug_set()
2442 old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; in intel_psr_debug_set()
2443 intel_dp->psr.debug = val; in intel_psr_debug_set()
2449 if (intel_dp->psr.enabled) in intel_psr_debug_set()
2452 mutex_unlock(&intel_dp->psr.lock); in intel_psr_debug_set()
2462 struct intel_psr *psr = &intel_dp->psr; in intel_psr_handle_irq()
2465 psr->sink_not_reliable = true; in intel_psr_handle_irq()
2467 drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); in intel_psr_handle_irq()
2475 mutex_lock(&intel_dp->psr.lock); in intel_psr_work()
2477 if (!intel_dp->psr.enabled) in intel_psr_work()
2480 if (READ_ONCE(intel_dp->psr.irq_aux_error)) in intel_psr_work()
2484 * We have to make sure PSR is ready for re-enable in intel_psr_work()
2487 * and be ready for re-enable. in intel_psr_work()
2497 if (intel_dp->psr.busy_frontbuffer_bits || intel_dp->psr.active) in intel_psr_work()
2502 mutex_unlock(&intel_dp->psr.lock); in intel_psr_work()
2508 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr_invalidate_handle()
2510 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_invalidate_handle()
2513 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_invalidate_handle()
2515 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in _psr_invalidate_handle()
2523 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in _psr_invalidate_handle()
2524 intel_dp->psr.psr2_sel_fetch_cff_enabled = true; in _psr_invalidate_handle()
2531 * intel_psr_invalidate - Invalidate PSR
2551 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_psr_invalidate()
2555 mutex_lock(&intel_dp->psr.lock); in intel_psr_invalidate()
2556 if (!intel_dp->psr.enabled) { in intel_psr_invalidate()
2557 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
2562 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_invalidate()
2563 intel_dp->psr.busy_frontbuffer_bits |= pipe_frontbuffer_bits; in intel_psr_invalidate()
2568 mutex_unlock(&intel_dp->psr.lock); in intel_psr_invalidate()
2583 if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || in tgl_dc3co_flush_locked()
2584 !intel_dp->psr.active) in tgl_dc3co_flush_locked()
2592 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe))) in tgl_dc3co_flush_locked()
2596 mod_delayed_work(i915->unordered_wq, &intel_dp->psr.dc3co_work, in tgl_dc3co_flush_locked()
2597 intel_dp->psr.dc3co_exit_delay); in tgl_dc3co_flush_locked()
2603 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in _psr_flush_handle()
2605 if (intel_dp->psr.psr2_sel_fetch_enabled) { in _psr_flush_handle()
2606 if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { in _psr_flush_handle()
2608 if (intel_dp->psr.busy_frontbuffer_bits == 0) { in _psr_flush_handle()
2622 intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); in _psr_flush_handle()
2623 intel_dp->psr.psr2_sel_fetch_cff_enabled = false; in _psr_flush_handle()
2635 if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) in _psr_flush_handle()
2636 queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); in _psr_flush_handle()
2641 * intel_psr_flush - Flush PSR
2658 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_psr_flush()
2662 mutex_lock(&intel_dp->psr.lock); in intel_psr_flush()
2663 if (!intel_dp->psr.enabled) { in intel_psr_flush()
2664 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2669 INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe); in intel_psr_flush()
2670 intel_dp->psr.busy_frontbuffer_bits &= ~pipe_frontbuffer_bits; in intel_psr_flush()
2677 if (intel_dp->psr.paused) in intel_psr_flush()
2682 !intel_dp->psr.psr2_sel_fetch_enabled)) { in intel_psr_flush()
2693 mutex_unlock(&intel_dp->psr.lock); in intel_psr_flush()
2698 * intel_psr_init - Init basic PSR work and mutex.
2707 struct intel_connector *connector = intel_dp->attached_connector; in intel_psr_init()
2723 if (DISPLAY_VER(dev_priv) < 12 && dig_port->base.port != PORT_A) { in intel_psr_init()
2724 drm_dbg_kms(&dev_priv->drm, in intel_psr_init()
2729 intel_dp->psr.source_support = true; in intel_psr_init()
2734 intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link; in intel_psr_init()
2736 INIT_WORK(&intel_dp->psr.work, intel_psr_work); in intel_psr_init()
2737 INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work); in intel_psr_init()
2738 mutex_init(&intel_dp->psr.lock); in intel_psr_init()
2744 struct drm_dp_aux *aux = &intel_dp->aux; in psr_get_status_and_error_status()
2763 struct drm_dp_aux *aux = &intel_dp->aux; in psr_alpm_check()
2764 struct intel_psr *psr = &intel_dp->psr; in psr_alpm_check()
2768 if (!psr->psr2_enabled) in psr_alpm_check()
2773 drm_err(&dev_priv->drm, "Error reading ALPM status\n"); in psr_alpm_check()
2779 psr->sink_not_reliable = true; in psr_alpm_check()
2780 drm_dbg_kms(&dev_priv->drm, in psr_alpm_check()
2791 struct intel_psr *psr = &intel_dp->psr; in psr_capability_changed_check()
2795 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ESI, &val); in psr_capability_changed_check()
2797 drm_err(&dev_priv->drm, "Error reading DP_PSR_ESI\n"); in psr_capability_changed_check()
2803 psr->sink_not_reliable = true; in psr_capability_changed_check()
2804 drm_dbg_kms(&dev_priv->drm, in psr_capability_changed_check()
2808 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ESI, val); in psr_capability_changed_check()
2815 struct intel_psr *psr = &intel_dp->psr; in intel_psr_short_pulse()
2824 mutex_lock(&psr->lock); in intel_psr_short_pulse()
2826 if (!psr->enabled) in intel_psr_short_pulse()
2830 drm_err(&dev_priv->drm, in intel_psr_short_pulse()
2837 psr->sink_not_reliable = true; in intel_psr_short_pulse()
2841 drm_dbg_kms(&dev_priv->drm, in intel_psr_short_pulse()
2844 drm_dbg_kms(&dev_priv->drm, in intel_psr_short_pulse()
2847 drm_dbg_kms(&dev_priv->drm, in intel_psr_short_pulse()
2850 drm_dbg_kms(&dev_priv->drm, in intel_psr_short_pulse()
2854 drm_err(&dev_priv->drm, in intel_psr_short_pulse()
2858 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, error_status); in intel_psr_short_pulse()
2864 mutex_unlock(&psr->lock); in intel_psr_short_pulse()
2874 mutex_lock(&intel_dp->psr.lock); in intel_psr_enabled()
2875 ret = intel_dp->psr.enabled; in intel_psr_enabled()
2876 mutex_unlock(&intel_dp->psr.lock); in intel_psr_enabled()
2882 * intel_psr_lock - grab PSR lock
2891 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_psr_lock()
2894 if (!crtc_state->has_psr) in intel_psr_lock()
2897 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, in intel_psr_lock()
2898 crtc_state->uapi.encoder_mask) { in intel_psr_lock()
2901 mutex_lock(&intel_dp->psr.lock); in intel_psr_lock()
2907 * intel_psr_unlock - release PSR lock
2914 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_psr_unlock()
2917 if (!crtc_state->has_psr) in intel_psr_unlock()
2920 for_each_intel_encoder_mask_with_psr(&i915->drm, encoder, in intel_psr_unlock()
2921 crtc_state->uapi.encoder_mask) { in intel_psr_unlock()
2924 mutex_unlock(&intel_dp->psr.lock); in intel_psr_unlock()
2933 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in psr_source_status()
2937 if (intel_dp->psr.psr2_enabled) { in psr_source_status()
2978 enum transcoder cpu_transcoder = intel_dp->psr.transcoder; in intel_psr_status()
2979 struct intel_psr *psr = &intel_dp->psr; in intel_psr_status()
2985 seq_printf(m, "Sink support: %s", str_yes_no(psr->sink_support)); in intel_psr_status()
2986 if (psr->sink_support) in intel_psr_status()
2987 seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); in intel_psr_status()
2990 if (!psr->sink_support) in intel_psr_status()
2993 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in intel_psr_status()
2994 mutex_lock(&psr->lock); in intel_psr_status()
2996 if (psr->enabled) in intel_psr_status()
2997 status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; in intel_psr_status()
3002 if (!psr->enabled) { in intel_psr_status()
3004 str_yes_no(psr->sink_not_reliable)); in intel_psr_status()
3009 if (psr->psr2_enabled) { in intel_psr_status()
3020 psr->busy_frontbuffer_bits); in intel_psr_status()
3029 if (psr->debug & I915_PSR_DEBUG_IRQ) { in intel_psr_status()
3031 psr->last_entry_attempt); in intel_psr_status()
3032 seq_printf(m, "Last exit at: %lld\n", psr->last_exit); in intel_psr_status()
3035 if (psr->psr2_enabled) { in intel_psr_status()
3060 str_enabled_disabled(psr->psr2_sel_fetch_enabled)); in intel_psr_status()
3064 mutex_unlock(&psr->lock); in intel_psr_status()
3065 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in intel_psr_status()
3072 struct drm_i915_private *dev_priv = m->private; in i915_edp_psr_status_show()
3077 return -ENODEV; in i915_edp_psr_status_show()
3080 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in i915_edp_psr_status_show()
3086 return -ENODEV; in i915_edp_psr_status_show()
3098 int ret = -ENODEV; in i915_edp_psr_debug_set()
3103 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in i915_edp_psr_debug_set()
3106 drm_dbg_kms(&dev_priv->drm, "Setting PSR debug to %llx\n", val); in i915_edp_psr_debug_set()
3108 wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); in i915_edp_psr_debug_set()
3113 intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); in i915_edp_psr_debug_set()
3126 return -ENODEV; in i915_edp_psr_debug_get()
3128 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in i915_edp_psr_debug_get()
3132 *val = READ_ONCE(intel_dp->psr.debug); in i915_edp_psr_debug_get()
3136 return -ENODEV; in i915_edp_psr_debug_get()
3145 struct drm_minor *minor = i915->drm.primary; in intel_psr_debugfs_register()
3147 debugfs_create_file("i915_edp_psr_debug", 0644, minor->debugfs_root, in intel_psr_debugfs_register()
3150 debugfs_create_file("i915_edp_psr_status", 0444, minor->debugfs_root, in intel_psr_debugfs_register()
3156 struct intel_connector *connector = m->private; in i915_psr_sink_status_show()
3163 "transition to inactive, capture and display, timing re-sync", in i915_psr_sink_status_show()
3174 return -ENODEV; in i915_psr_sink_status_show()
3177 if (connector->base.status != connector_status_connected) in i915_psr_sink_status_show()
3178 return -ENODEV; in i915_psr_sink_status_show()
3180 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val); in i915_psr_sink_status_show()
3182 return ret < 0 ? ret : -EIO; in i915_psr_sink_status_show()
3198 struct intel_connector *connector = m->private; in i915_psr_status_show()
3207 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_psr_connector_debugfs_add()
3208 struct dentry *root = connector->base.debugfs_entry; in intel_psr_connector_debugfs_add()
3210 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) in intel_psr_connector_debugfs_add()