26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
102 /* DCLRKM (dst-key) register */
172 	u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
174 	u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
176 	u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
178 	u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
180 	u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
192 	u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
195 	u32 brightness, contrast, saturation;  member
209 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);  in i830_overlay_clock_gating()
220 	pci_bus_read_config_byte(pdev->bus,  in i830_overlay_clock_gating()
226 	pci_bus_write_config_byte(pdev->bus,  in i830_overlay_clock_gating()
236 	overlay->flip_complete = fn;  in alloc_request()
238 	rq = i915_request_create(overlay->context);  in alloc_request()
242 	err = i915_active_add_request(&overlay->last_flip, rq);  in alloc_request()
254 	struct drm_i915_private *dev_priv = overlay->i915;  in intel_overlay_on()
258 	drm_WARN_ON(&dev_priv->drm, overlay->active);  in intel_overlay_on()
270 	overlay->active = true;  in intel_overlay_on()
276 	*cs++ = overlay->flip_addr | OFC_UPDATE;  in intel_overlay_on()
283 	return i915_active_wait(&overlay->last_flip);  in intel_overlay_on()
289 	enum pipe pipe = overlay->crtc->pipe;  in intel_overlay_flip_prepare()
292 	drm_WARN_ON(&overlay->i915->drm, overlay->old_vma);  in intel_overlay_flip_prepare()
295 		frontbuffer = intel_frontbuffer_get(vma->obj);  in intel_overlay_flip_prepare()
297 	intel_frontbuffer_track(overlay->frontbuffer, frontbuffer,  in intel_overlay_flip_prepare()
300 	if (overlay->frontbuffer)  in intel_overlay_flip_prepare()
301 		intel_frontbuffer_put(overlay->frontbuffer);  in intel_overlay_flip_prepare()
302 	overlay->frontbuffer = frontbuffer;  in intel_overlay_flip_prepare()
304 	intel_frontbuffer_flip_prepare(overlay->i915,  in intel_overlay_flip_prepare()
307 	overlay->old_vma = overlay->vma;  in intel_overlay_flip_prepare()
309 		overlay->vma = i915_vma_get(vma);  in intel_overlay_flip_prepare()
311 		overlay->vma = NULL;  in intel_overlay_flip_prepare()
319 	struct drm_i915_private *dev_priv = overlay->i915;  in intel_overlay_continue()
321 	u32 flip_addr = overlay->flip_addr;  in intel_overlay_continue()
324 	drm_WARN_ON(&dev_priv->drm, !overlay->active);  in intel_overlay_continue()
332 		drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp);  in intel_overlay_continue()
358 	vma = fetch_and_zero(&overlay->old_vma);  in intel_overlay_release_old_vma()
359 	if (drm_WARN_ON(&overlay->i915->drm, !vma))  in intel_overlay_release_old_vma()
362 	intel_frontbuffer_flip_complete(overlay->i915,  in intel_overlay_release_old_vma()
363 					INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));  in intel_overlay_release_old_vma()
377 	struct drm_i915_private *dev_priv = overlay->i915;  in intel_overlay_off_tail()
381 	overlay->crtc->overlay = NULL;  in intel_overlay_off_tail()
382 	overlay->crtc = NULL;  in intel_overlay_off_tail()
383 	overlay->active = false;  in intel_overlay_off_tail()
394 	if (overlay->flip_complete)  in intel_overlay_last_flip_retire()
395 		overlay->flip_complete(overlay);  in intel_overlay_last_flip_retire()
402 	u32 *cs, flip_addr = overlay->flip_addr;  in intel_overlay_off()
404 	drm_WARN_ON(&overlay->i915->drm, !overlay->active);  in intel_overlay_off()
437 	return i915_active_wait(&overlay->last_flip);  in intel_overlay_off()
444 	return i915_active_wait(&overlay->last_flip);  in intel_overlay_recover_from_interrupt()
453 	struct drm_i915_private *dev_priv = overlay->i915;  in intel_overlay_release_old_vid()
461 	if (!overlay->old_vma)  in intel_overlay_release_old_vid()
485 	return i915_active_wait(&overlay->last_flip);  in intel_overlay_release_old_vid()
490 	struct intel_overlay *overlay = dev_priv->display.overlay;  in intel_overlay_reset()
495 	overlay->old_xscale = 0;  in intel_overlay_reset()
496 	overlay->old_yscale = 0;  in intel_overlay_reset()
497 	overlay->crtc = NULL;  in intel_overlay_reset()
498 	overlay->active = false;  in intel_overlay_reset()
509 		return -EINVAL;  in packed_depth_bytes()
519 		return -EINVAL;  in packed_width_bytes()
533 		return -EINVAL;  in uv_hsubsampling()
547 		return -EINVAL;  in uv_vsubsampling()
563 	return (sw - 32) >> 3;  in calc_swidthsw()
608 	memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));  in update_polyphase_filter()
609 	memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,  in update_polyphase_filter()
622 	int uv_hscale = uv_hsubsampling(params->flags);  in update_scaling_factors()
623 	int uv_vscale = uv_vsubsampling(params->flags);  in update_scaling_factors()
625 	if (params->dst_width > 1)  in update_scaling_factors()
626 		xscale = ((params->src_scan_width - 1) << FP_SHIFT) /  in update_scaling_factors()
627 			params->dst_width;  in update_scaling_factors()
631 	if (params->dst_height > 1)  in update_scaling_factors()
632 		yscale = ((params->src_scan_height - 1) << FP_SHIFT) /  in update_scaling_factors()
633 			params->dst_height;  in update_scaling_factors()
637 	/*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/  in update_scaling_factors()
640 	/* make the Y scale to UV scale ratio an exact multiply */  in update_scaling_factors()
648 	if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)  in update_scaling_factors()
650 	overlay->old_xscale = xscale;  in update_scaling_factors()
651 	overlay->old_yscale = yscale;  in update_scaling_factors()
656 		 &regs->YRGBSCALE);  in update_scaling_factors()
661 		 &regs->UVSCALE);  in update_scaling_factors()
665 		 &regs->UVSCALEV);  in update_scaling_factors()
677 		to_intel_plane_state(overlay->crtc->base.primary->state);  in update_colorkey()
678 	u32 key = overlay->color_key;  in update_colorkey()
682 	if (overlay->color_key_enabled)  in update_colorkey()
685 	if (state->uapi.visible)  in update_colorkey()
686 		format = state->hw.fb->format->format;  in update_colorkey()
711 	iowrite32(key, &regs->DCLRKV);  in update_colorkey()
712 	iowrite32(flags, &regs->DCLRKM);  in update_colorkey()
719 	if (params->flags & I915_OVERLAY_YUV_PLANAR) {  in overlay_cmd_reg()
720 		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {  in overlay_cmd_reg()
733 		switch (params->flags & I915_OVERLAY_DEPTH_MASK) {  in overlay_cmd_reg()
742 		switch (params->flags & I915_OVERLAY_SWAP_MASK) {  in overlay_cmd_reg()
774 	if (ret == -EDEADLK) {  in intel_overlay_pin_fb()
790 	struct overlay_registers __iomem *regs = overlay->regs;  in intel_overlay_do_put_image()
791 	struct drm_i915_private *dev_priv = overlay->i915;  in intel_overlay_do_put_image()
793 	enum pipe pipe = overlay->crtc->pipe;  in intel_overlay_do_put_image()
798 	drm_WARN_ON(&dev_priv->drm,  in intel_overlay_do_put_image()
799 		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));  in intel_overlay_do_put_image()
805 	atomic_inc(&dev_priv->gpu_error.pending_fb_pin);  in intel_overlay_do_put_image()
815 	if (!overlay->active) {  in intel_overlay_do_put_image()
817 			overlay->crtc->config;  in intel_overlay_do_put_image()
820 		if (crtc_state->gamma_enable &&  in intel_overlay_do_put_image()
821 		    crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)  in intel_overlay_do_put_image()
823 		if (crtc_state->gamma_enable)  in intel_overlay_do_put_image()
829 		iowrite32(oconfig, &regs->OCONFIG);  in intel_overlay_do_put_image()
836 	iowrite32(params->dst_y << 16 | params->dst_x, &regs->DWINPOS);  in intel_overlay_do_put_image()
837 	iowrite32(params->dst_height << 16 | params->dst_width, &regs->DWINSZ);  in intel_overlay_do_put_image()
839 	if (params->flags & I915_OVERLAY_YUV_PACKED)  in intel_overlay_do_put_image()
840 		tmp_width = packed_width_bytes(params->flags,  in intel_overlay_do_put_image()
841 					       params->src_width);  in intel_overlay_do_put_image()
843 		tmp_width = params->src_width;  in intel_overlay_do_put_image()
845 	swidth = params->src_width;  in intel_overlay_do_put_image()
846 	swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);  in intel_overlay_do_put_image()
847 	sheight = params->src_height;  in intel_overlay_do_put_image()
848 	iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);  in intel_overlay_do_put_image()
849 	ostride = params->stride_Y;  in intel_overlay_do_put_image()
851 	if (params->flags & I915_OVERLAY_YUV_PLANAR) {  in intel_overlay_do_put_image()
852 		int uv_hscale = uv_hsubsampling(params->flags);  in intel_overlay_do_put_image()
853 		int uv_vscale = uv_vsubsampling(params->flags);  in intel_overlay_do_put_image()
856 		swidth |= (params->src_width / uv_hscale) << 16;  in intel_overlay_do_put_image()
857 		sheight |= (params->src_height / uv_vscale) << 16;  in intel_overlay_do_put_image()
859 		tmp_U = calc_swidthsw(dev_priv, params->offset_U,  in intel_overlay_do_put_image()
860 				      params->src_width / uv_hscale);  in intel_overlay_do_put_image()
861 		tmp_V = calc_swidthsw(dev_priv, params->offset_V,  in intel_overlay_do_put_image()
862 				      params->src_width / uv_hscale);  in intel_overlay_do_put_image()
865 		iowrite32(i915_ggtt_offset(vma) + params->offset_U,  in intel_overlay_do_put_image()
866 			  &regs->OBUF_0U);  in intel_overlay_do_put_image()
867 		iowrite32(i915_ggtt_offset(vma) + params->offset_V,  in intel_overlay_do_put_image()
868 			  &regs->OBUF_0V);  in intel_overlay_do_put_image()
870 		ostride |= params->stride_UV << 16;  in intel_overlay_do_put_image()
873 	iowrite32(swidth, &regs->SWIDTH);  in intel_overlay_do_put_image()
874 	iowrite32(swidthsw, &regs->SWIDTHSW);  in intel_overlay_do_put_image()
875 	iowrite32(sheight, &regs->SHEIGHT);  in intel_overlay_do_put_image()
876 	iowrite32(ostride, &regs->OSTRIDE);  in intel_overlay_do_put_image()
882 	iowrite32(overlay_cmd_reg(params), &regs->OCMD);  in intel_overlay_do_put_image()
893 	atomic_dec(&dev_priv->gpu_error.pending_fb_pin);  in intel_overlay_do_put_image()
900 	struct drm_i915_private *dev_priv = overlay->i915;  in intel_overlay_switch_off()
903 	drm_WARN_ON(&dev_priv->drm,  in intel_overlay_switch_off()
904 		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));  in intel_overlay_switch_off()
910 	if (!overlay->active)  in intel_overlay_switch_off()
917 	iowrite32(0, &overlay->regs->OCMD);  in intel_overlay_switch_off()
925 	if (!crtc->active)  in check_overlay_possible_on_crtc()
926 		return -EINVAL;  in check_overlay_possible_on_crtc()
929 	if (crtc->config->double_wide)  in check_overlay_possible_on_crtc()
930 		return -EINVAL;  in check_overlay_possible_on_crtc()
937 	struct drm_i915_private *dev_priv = overlay->i915;  in update_pfit_vscale_ratio()
938 	u32 ratio;  in update_pfit_vscale_ratio()  local
947 		ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp);  in update_pfit_vscale_ratio()
956 		ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp);  in update_pfit_vscale_ratio()
959 	overlay->pfit_vscale_ratio = ratio;  in update_pfit_vscale_ratio()
966 		overlay->crtc->config;  in check_overlay_dst()
969 	drm_rect_init(&req, rec->dst_x, rec->dst_y,  in check_overlay_dst()
970 		      rec->dst_width, rec->dst_height);  in check_overlay_dst()
973 	drm_rect_intersect(&clipped, &crtc_state->pipe_src);  in check_overlay_dst()
977 		return -EINVAL;  in check_overlay_dst()
987 	tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;  in check_overlay_scaling()
989 		return -EINVAL;  in check_overlay_scaling()
991 	tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;  in check_overlay_scaling()
993 		return -EINVAL;  in check_overlay_scaling()
1002 	int uv_hscale = uv_hsubsampling(rec->flags);  in check_overlay_src()
1003 	int uv_vscale = uv_vsubsampling(rec->flags);  in check_overlay_src()
1010 		if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||  in check_overlay_src()
1011 		    rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)  in check_overlay_src()
1012 			return -EINVAL;  in check_overlay_src()
1014 		if (rec->src_height > IMAGE_MAX_HEIGHT ||  in check_overlay_src()
1015 		    rec->src_width  > IMAGE_MAX_WIDTH)  in check_overlay_src()
1016 			return -EINVAL;  in check_overlay_src()
1019 	/* better safe than sorry, use 4 as the maximal subsampling ratio */  in check_overlay_src()
1020 	if (rec->src_height < N_VERT_Y_TAPS*4 ||  in check_overlay_src()
1021 	    rec->src_width  < N_HORIZ_Y_TAPS*4)  in check_overlay_src()
1022 		return -EINVAL;  in check_overlay_src()
1025 	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {  in check_overlay_src()
1028 		return -EINVAL;  in check_overlay_src()
1032 			return -EINVAL;  in check_overlay_src()
1034 		depth = packed_depth_bytes(rec->flags);  in check_overlay_src()
1039 		rec->stride_UV = 0;  in check_overlay_src()
1040 		rec->offset_U = 0;  in check_overlay_src()
1041 		rec->offset_V = 0;  in check_overlay_src()
1043 		if (rec->offset_Y % depth)  in check_overlay_src()
1044 			return -EINVAL;  in check_overlay_src()
1049 			return -EINVAL;  in check_overlay_src()
1054 		return -EINVAL;  in check_overlay_src()
1057 	if (rec->src_width % uv_hscale)  in check_overlay_src()
1058 		return -EINVAL;  in check_overlay_src()
1066 	if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)  in check_overlay_src()
1067 		return -EINVAL;  in check_overlay_src()
1068 	if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512)  in check_overlay_src()
1069 		return -EINVAL;  in check_overlay_src()
1071 	tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?  in check_overlay_src()
1073 	if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)  in check_overlay_src()
1074 		return -EINVAL;  in check_overlay_src()
1077 	switch (rec->flags & I915_OVERLAY_TYPE_MASK) {  in check_overlay_src()
1081 		if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)  in check_overlay_src()
1082 			return -EINVAL;  in check_overlay_src()
1084 		tmp = rec->stride_Y*rec->src_height;  in check_overlay_src()
1085 		if (rec->offset_Y + tmp > new_bo->base.size)  in check_overlay_src()
1086 			return -EINVAL;  in check_overlay_src()
1090 		if (rec->src_width > rec->stride_Y)  in check_overlay_src()
1091 			return -EINVAL;  in check_overlay_src()
1092 		if (rec->src_width/uv_hscale > rec->stride_UV)  in check_overlay_src()
1093 			return -EINVAL;  in check_overlay_src()
1095 		tmp = rec->stride_Y * rec->src_height;  in check_overlay_src()
1096 		if (rec->offset_Y + tmp > new_bo->base.size)  in check_overlay_src()
1097 			return -EINVAL;  in check_overlay_src()
1099 		tmp = rec->stride_UV * (rec->src_height / uv_vscale);  in check_overlay_src()
1100 		if (rec->offset_U + tmp > new_bo->base.size ||  in check_overlay_src()
1101 		    rec->offset_V + tmp > new_bo->base.size)  in check_overlay_src()
1102 			return -EINVAL;  in check_overlay_src()
1120 	overlay = dev_priv->display.overlay;  in intel_overlay_put_image_ioctl()
1122 		drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");  in intel_overlay_put_image_ioctl()
1123 		return -ENODEV;  in intel_overlay_put_image_ioctl()
1126 	if (!(params->flags & I915_OVERLAY_ENABLE)) {  in intel_overlay_put_image_ioctl()
1134 	drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);  in intel_overlay_put_image_ioctl()
1136 		return -ENOENT;  in intel_overlay_put_image_ioctl()
1139 	new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);  in intel_overlay_put_image_ioctl()
1141 		return -ENOENT;  in intel_overlay_put_image_ioctl()
1146 		drm_dbg_kms(&dev_priv->drm,  in intel_overlay_put_image_ioctl()
1148 		ret = -EINVAL;  in intel_overlay_put_image_ioctl()
1156 	if (overlay->crtc != crtc) {  in intel_overlay_put_image_ioctl()
1165 		overlay->crtc = crtc;  in intel_overlay_put_image_ioctl()
1166 		crtc->overlay = overlay;  in intel_overlay_put_image_ioctl()
1168 		/* line too wide, i.e. one-line-mode */  in intel_overlay_put_image_ioctl()
1169 		if (drm_rect_width(&crtc->config->pipe_src) > 1024 &&  in intel_overlay_put_image_ioctl()
1170 		    crtc->config->gmch_pfit.control & PFIT_ENABLE) {  in intel_overlay_put_image_ioctl()
1171 			overlay->pfit_active = true;  in intel_overlay_put_image_ioctl()
1174 			overlay->pfit_active = false;  in intel_overlay_put_image_ioctl()
1181 	if (overlay->pfit_active) {  in intel_overlay_put_image_ioctl()
1182 		params->dst_y = (((u32)params->dst_y << 12) /  in intel_overlay_put_image_ioctl()
1183 				 overlay->pfit_vscale_ratio);  in intel_overlay_put_image_ioctl()
1185 		params->dst_height = (((u32)params->dst_height << 12) /  in intel_overlay_put_image_ioctl()
1186 				 overlay->pfit_vscale_ratio) + 1;  in intel_overlay_put_image_ioctl()
1189 	if (params->src_scan_height > params->src_height ||  in intel_overlay_put_image_ioctl()
1190 	    params->src_scan_width > params->src_width) {  in intel_overlay_put_image_ioctl()
1191 		ret = -EINVAL;  in intel_overlay_put_image_ioctl()
1199 	/* Check scaling after src size to prevent a divide-by-zero. */  in intel_overlay_put_image_ioctl()
1223 	iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),  in update_reg_attrs()
1224 		  &regs->OCLRC0);  in update_reg_attrs()
1225 	iowrite32(overlay->saturation, &regs->OCLRC1);  in update_reg_attrs()
1257 	if (!check_gamma_bounds(0, attrs->gamma0) ||  in check_gamma()
1258 	    !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||  in check_gamma()
1259 	    !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||  in check_gamma()
1260 	    !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||  in check_gamma()
1261 	    !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||  in check_gamma()
1262 	    !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||  in check_gamma()
1263 	    !check_gamma_bounds(attrs->gamma5, 0x00ffffff))  in check_gamma()
1264 		return -EINVAL;  in check_gamma()
1266 	if (!check_gamma5_errata(attrs->gamma5))  in check_gamma()
1267 		return -EINVAL;  in check_gamma()
1280 	overlay = dev_priv->display.overlay;  in intel_overlay_attrs_ioctl()
1282 		drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");  in intel_overlay_attrs_ioctl()
1283 		return -ENODEV;  in intel_overlay_attrs_ioctl()
1288 	ret = -EINVAL;  in intel_overlay_attrs_ioctl()
1289 	if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {  in intel_overlay_attrs_ioctl()
1290 		attrs->color_key  = overlay->color_key;  in intel_overlay_attrs_ioctl()
1291 		attrs->brightness = overlay->brightness;  in intel_overlay_attrs_ioctl()
1292 		attrs->contrast   = overlay->contrast;  in intel_overlay_attrs_ioctl()
1293 		attrs->saturation = overlay->saturation;  in intel_overlay_attrs_ioctl()
1296 			attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);  in intel_overlay_attrs_ioctl()
1297 			attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);  in intel_overlay_attrs_ioctl()
1298 			attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);  in intel_overlay_attrs_ioctl()
1299 			attrs->gamma3 = intel_de_read(dev_priv, OGAMC3);  in intel_overlay_attrs_ioctl()
1300 			attrs->gamma4 = intel_de_read(dev_priv, OGAMC4);  in intel_overlay_attrs_ioctl()
1301 			attrs->gamma5 = intel_de_read(dev_priv, OGAMC5);  in intel_overlay_attrs_ioctl()
1304 		if (attrs->brightness < -128 || attrs->brightness > 127)  in intel_overlay_attrs_ioctl()
1306 		if (attrs->contrast > 255)  in intel_overlay_attrs_ioctl()
1308 		if (attrs->saturation > 1023)  in intel_overlay_attrs_ioctl()
1311 		overlay->color_key  = attrs->color_key;  in intel_overlay_attrs_ioctl()
1312 		overlay->brightness = attrs->brightness;  in intel_overlay_attrs_ioctl()
1313 		overlay->contrast   = attrs->contrast;  in intel_overlay_attrs_ioctl()
1314 		overlay->saturation = attrs->saturation;  in intel_overlay_attrs_ioctl()
1316 		update_reg_attrs(overlay, overlay->regs);  in intel_overlay_attrs_ioctl()
1318 		if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {  in intel_overlay_attrs_ioctl()
1322 			if (overlay->active) {  in intel_overlay_attrs_ioctl()
1323 				ret = -EBUSY;  in intel_overlay_attrs_ioctl()
1331 			intel_de_write(dev_priv, OGAMC0, attrs->gamma0);  in intel_overlay_attrs_ioctl()
1332 			intel_de_write(dev_priv, OGAMC1, attrs->gamma1);  in intel_overlay_attrs_ioctl()
1333 			intel_de_write(dev_priv, OGAMC2, attrs->gamma2);  in intel_overlay_attrs_ioctl()
1334 			intel_de_write(dev_priv, OGAMC3, attrs->gamma3);  in intel_overlay_attrs_ioctl()
1335 			intel_de_write(dev_priv, OGAMC4, attrs->gamma4);  in intel_overlay_attrs_ioctl()
1336 			intel_de_write(dev_priv, OGAMC5, attrs->gamma5);  in intel_overlay_attrs_ioctl()
1339 	overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;  in intel_overlay_attrs_ioctl()
1350 	struct drm_i915_private *i915 = overlay->i915;  in get_registers()
1351 	struct drm_i915_gem_object *obj = ERR_PTR(-ENODEV);  in get_registers()
1369 		overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);  in get_registers()
1371 		overlay->flip_addr = i915_ggtt_offset(vma);  in get_registers()
1372 	overlay->regs = i915_vma_pin_iomap(vma);  in get_registers()
1375 	if (IS_ERR(overlay->regs)) {  in get_registers()
1376 		err = PTR_ERR(overlay->regs);  in get_registers()
1380 	overlay->reg_bo = obj;  in get_registers()
1397 	engine = to_gt(dev_priv)->engine[RCS0];  in intel_overlay_setup()
1398 	if (!engine || !engine->kernel_context)  in intel_overlay_setup()
1405 	overlay->i915 = dev_priv;  in intel_overlay_setup()
1406 	overlay->context = engine->kernel_context;  in intel_overlay_setup()
1407 	overlay->color_key = 0x0101fe;  in intel_overlay_setup()
1408 	overlay->color_key_enabled = true;  in intel_overlay_setup()
1409 	overlay->brightness = -19;  in intel_overlay_setup()
1410 	overlay->contrast = 75;  in intel_overlay_setup()
1411 	overlay->saturation = 146;  in intel_overlay_setup()
1413 	i915_active_init(&overlay->last_flip,  in intel_overlay_setup()
1420 	memset_io(overlay->regs, 0, sizeof(struct overlay_registers));  in intel_overlay_setup()
1421 	update_polyphase_filter(overlay->regs);  in intel_overlay_setup()
1422 	update_reg_attrs(overlay, overlay->regs);  in intel_overlay_setup()
1424 	dev_priv->display.overlay = overlay;  in intel_overlay_setup()
1425 	drm_info(&dev_priv->drm, "Initialized overlay support.\n");  in intel_overlay_setup()
1436 	overlay = fetch_and_zero(&dev_priv->display.overlay);  in intel_overlay_cleanup()
1445 	drm_WARN_ON(&dev_priv->drm, overlay->active);  in intel_overlay_cleanup()
1447 	i915_gem_object_put(overlay->reg_bo);  in intel_overlay_cleanup()
1448 	i915_active_fini(&overlay->last_flip);  in intel_overlay_cleanup()
1465 	struct intel_overlay *overlay = dev_priv->display.overlay;  in intel_overlay_capture_error_state()
1468 	if (!overlay || !overlay->active)  in intel_overlay_capture_error_state()
1475 	error->dovsta = intel_de_read(dev_priv, DOVSTA);  in intel_overlay_capture_error_state()
1476 	error->isr = intel_de_read(dev_priv, GEN2_ISR);  in intel_overlay_capture_error_state()
1477 	error->base = overlay->flip_addr;  in intel_overlay_capture_error_state()
1479 	memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));  in intel_overlay_capture_error_state()
1489 			  error->dovsta, error->isr);  in intel_overlay_print_error_state()
1491 			  error->base);  in intel_overlay_print_error_state()
1493 #define P(x) i915_error_printf(m, "    " #x ":	0x%08x\n", error->regs.x)  in intel_overlay_print_error_state()