629 	intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll);  in hsw_ddi_wrpll_enable()
688 	hw_state->wrpll = val;  in hsw_ddi_wrpll_get_hw_state()
927 	u32 wrpll = pll_state->wrpll;  in hsw_ddi_wrpll_get_freq()  local
929 	switch (wrpll & WRPLL_REF_MASK) {  in hsw_ddi_wrpll_get_freq()
949 		MISSING_CASE(wrpll);  in hsw_ddi_wrpll_get_freq()
953 	r = wrpll & WRPLL_DIVIDER_REF_MASK;  in hsw_ddi_wrpll_get_freq()
954 	p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;  in hsw_ddi_wrpll_get_freq()
955 	n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;  in hsw_ddi_wrpll_get_freq()
972 	crtc_state->dpll_hw_state.wrpll =  in hsw_ddi_wrpll_compute_dpll()
1177 		    hw_state->wrpll, hw_state->spll);  in hsw_dump_hw_state()
2473 	struct skl_wrpll_params wrpll;  member
2570 			*pll_params = params[i].wrpll;  in icl_calc_dp_combo_pll()