1394 	u64 dco_freq;			/* chosen dco freq */  member
1404 				  u64 dco_freq,  in skl_wrpll_try_divider()  argument
1409 	deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),  in skl_wrpll_try_divider()
1413 	if (dco_freq >= central_freq) {  in skl_wrpll_try_divider()
1418 			ctx->dco_freq = dco_freq;  in skl_wrpll_try_divider()
1426 		ctx->dco_freq = dco_freq;  in skl_wrpll_try_divider()
1496 	u64 dco_freq;  in skl_wrpll_params_populate()  local
1546 	dco_freq = p0 * p1 * p2 * afe_clock;  in skl_wrpll_params_populate()
1552 	params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1));  in skl_wrpll_params_populate()
1554 		div_u64((div_u64(dco_freq, ref_clock / KHz(1)) -  in skl_wrpll_params_populate()
1590 				u64 dco_freq = p * afe_clock;  in skl_ddi_calculate_wrpll()  local
1594 						      dco_freq,  in skl_ddi_calculate_wrpll()
1635 	u32 p0, p1, p2, dco_freq;  in skl_ddi_wrpll_get_freq()  local
1689 	dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *  in skl_ddi_wrpll_get_freq()
1692 	dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *  in skl_ddi_wrpll_get_freq()
1698 	return dco_freq / (p0 * p1 * p2 * 5);  in skl_ddi_wrpll_get_freq()
2411 				      u32 dco_freq, u32 ref_freq,  in icl_wrpll_params_populate()  argument
2452 	dco = div_u64((u64)dco_freq << 15, ref_freq);  in icl_wrpll_params_populate()
2692 	u32 p0, p1, p2, dco_freq;  in icl_ddi_combo_pll_get_freq()  local
2730 	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *  in icl_ddi_combo_pll_get_freq()
2739 	dco_freq += (dco_fraction * ref_clock) / 0x8000;  in icl_ddi_combo_pll_get_freq()
2744 	return dco_freq / (p0 * p1 * p2 * 5);  in icl_ddi_combo_pll_get_freq()