Lines Matching full:dpll
313 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
325 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
327 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
330 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
342 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
354 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
373 const struct dpll *clock) in intel_pll_is_valid()
444 const struct dpll *match_clock, in i9xx_find_best_dpll()
445 struct dpll *best_clock) in i9xx_find_best_dpll()
448 struct dpll clock; in i9xx_find_best_dpll()
502 const struct dpll *match_clock, in pnv_find_best_dpll()
503 struct dpll *best_clock) in pnv_find_best_dpll()
506 struct dpll clock; in pnv_find_best_dpll()
558 const struct dpll *match_clock, in g4x_find_best_dpll()
559 struct dpll *best_clock) in g4x_find_best_dpll()
562 struct dpll clock; in g4x_find_best_dpll()
609 const struct dpll *calculated_clock, in vlv_PLL_is_optimal()
610 const struct dpll *best_clock, in vlv_PLL_is_optimal()
652 const struct dpll *match_clock, in vlv_find_best_dpll()
653 struct dpll *best_clock) in vlv_find_best_dpll()
657 struct dpll clock; in vlv_find_best_dpll()
710 const struct dpll *match_clock, in chv_find_best_dpll()
711 struct dpll *best_clock) in chv_find_best_dpll()
716 struct dpll clock; in chv_find_best_dpll()
766 struct dpll *best_clock) in bxt_find_best_dpll()
776 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument
778 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp()
781 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) in pnv_dpll_compute_fp() argument
783 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
787 const struct dpll *clock, in i9xx_update_pll_dividers()
788 const struct dpll *reduced_clock) in i9xx_update_pll_dividers()
807 const struct dpll *clock, in i9xx_compute_dpll()
808 const struct dpll *reduced_clock) in i9xx_compute_dpll()
812 u32 dpll; in i9xx_compute_dpll() local
816 dpll = DPLL_VGA_MODE_DIS; in i9xx_compute_dpll()
819 dpll |= DPLLB_MODE_LVDS; in i9xx_compute_dpll()
821 dpll |= DPLLB_MODE_DAC_SERIAL; in i9xx_compute_dpll()
825 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_compute_dpll()
831 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
834 dpll |= DPLL_SDVO_HIGH_SPEED; in i9xx_compute_dpll()
838 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
839 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
841 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_compute_dpll()
844 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_compute_dpll()
850 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in i9xx_compute_dpll()
853 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in i9xx_compute_dpll()
856 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in i9xx_compute_dpll()
859 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in i9xx_compute_dpll()
865 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); in i9xx_compute_dpll()
868 dpll |= PLL_REF_INPUT_TVCLKINBC; in i9xx_compute_dpll()
871 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i9xx_compute_dpll()
873 dpll |= PLL_REF_INPUT_DREFCLK; in i9xx_compute_dpll()
875 dpll |= DPLL_VCO_ENABLE; in i9xx_compute_dpll()
876 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
886 const struct dpll *clock, in i8xx_compute_dpll()
887 const struct dpll *reduced_clock) in i8xx_compute_dpll()
891 u32 dpll; in i8xx_compute_dpll() local
895 dpll = DPLL_VGA_MODE_DIS; in i8xx_compute_dpll()
898 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
901 dpll |= PLL_P1_DIVIDE_BY_TWO; in i8xx_compute_dpll()
903 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_compute_dpll()
905 dpll |= PLL_P2_DIVIDE_BY_4; in i8xx_compute_dpll()
914 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock in i8xx_compute_dpll()
915 * Enable) must be set to “1” in both the DPLL A Control Register in i8xx_compute_dpll()
916 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." in i8xx_compute_dpll()
924 dpll |= DPLL_DVO_2X_MODE; in i8xx_compute_dpll()
928 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in i8xx_compute_dpll()
930 dpll |= PLL_REF_INPUT_DREFCLK; in i8xx_compute_dpll()
932 dpll |= DPLL_VCO_ENABLE; in i8xx_compute_dpll()
933 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
1025 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) in ilk_needs_fb_cb_tune() argument
1027 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune()
1031 const struct dpll *clock, in ilk_update_pll_dividers()
1032 const struct dpll *reduced_clock) in ilk_update_pll_dividers()
1064 const struct dpll *clock, in ilk_compute_dpll()
1065 const struct dpll *reduced_clock) in ilk_compute_dpll()
1069 u32 dpll; in ilk_compute_dpll() local
1073 dpll = 0; in ilk_compute_dpll()
1076 dpll |= DPLLB_MODE_LVDS; in ilk_compute_dpll()
1078 dpll |= DPLLB_MODE_DAC_SERIAL; in ilk_compute_dpll()
1080 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_compute_dpll()
1085 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1088 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1093 * possible to share the DPLL between CRT and HDMI. Enabling in ilk_compute_dpll()
1098 * DPLLs and so DPLL sharing is the only way to get three pipes in ilk_compute_dpll()
1100 * and potentially avoid enabling the second DPLL, but it's not in ilk_compute_dpll()
1102 * this on ILK at all since it has a fixed DPLL<->pipe mapping. in ilk_compute_dpll()
1106 dpll |= DPLL_SDVO_HIGH_SPEED; in ilk_compute_dpll()
1109 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1111 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_compute_dpll()
1115 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in ilk_compute_dpll()
1118 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in ilk_compute_dpll()
1121 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; in ilk_compute_dpll()
1124 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; in ilk_compute_dpll()
1131 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; in ilk_compute_dpll()
1133 dpll |= PLL_REF_INPUT_DREFCLK; in ilk_compute_dpll()
1135 dpll |= DPLL_VCO_ENABLE; in ilk_compute_dpll()
1137 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1179 refclk, NULL, &crtc_state->dpll)) in ilk_crtc_compute_clock()
1182 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1183 &crtc_state->dpll); in ilk_crtc_compute_clock()
1189 crtc_state->port_clock = crtc_state->dpll.dot; in ilk_crtc_compute_clock()
1212 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1215 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
1217 /* DPLL not used with DSI, but still need the rest set up */ in vlv_compute_dpll()
1219 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | in vlv_compute_dpll()
1230 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | in chv_compute_dpll()
1233 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in chv_compute_dpll()
1235 /* DPLL not used with DSI, but still need the rest set up */ in chv_compute_dpll()
1237 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; in chv_compute_dpll()
1253 refclk, NULL, &crtc_state->dpll)) in chv_crtc_compute_clock()
1262 crtc_state->port_clock = crtc_state->dpll.dot; in chv_crtc_compute_clock()
1278 refclk, NULL, &crtc_state->dpll)) { in vlv_crtc_compute_clock()
1288 crtc_state->port_clock = crtc_state->dpll.dot; in vlv_crtc_compute_clock()
1327 refclk, NULL, &crtc_state->dpll)) in g4x_crtc_compute_clock()
1330 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1331 &crtc_state->dpll); in g4x_crtc_compute_clock()
1333 crtc_state->port_clock = crtc_state->dpll.dot; in g4x_crtc_compute_clock()
1365 refclk, NULL, &crtc_state->dpll)) in pnv_crtc_compute_clock()
1368 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1369 &crtc_state->dpll); in pnv_crtc_compute_clock()
1371 crtc_state->port_clock = crtc_state->dpll.dot; in pnv_crtc_compute_clock()
1401 refclk, NULL, &crtc_state->dpll)) in i9xx_crtc_compute_clock()
1404 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1405 &crtc_state->dpll); in i9xx_crtc_compute_clock()
1407 crtc_state->port_clock = crtc_state->dpll.dot; in i9xx_crtc_compute_clock()
1441 refclk, NULL, &crtc_state->dpll)) in i8xx_crtc_compute_clock()
1444 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
1445 &crtc_state->dpll); in i8xx_crtc_compute_clock()
1447 crtc_state->port_clock = crtc_state->dpll.dot; in i8xx_crtc_compute_clock()
1511 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); in intel_dpll_crtc_compute_clock()
1513 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", in intel_dpll_crtc_compute_clock()
1535 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) in intel_dpll_crtc_get_shared_dpll()
1538 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); in intel_dpll_crtc_get_shared_dpll()
1540 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", in intel_dpll_crtc_get_shared_dpll()
1552 dev_priv->display.funcs.dpll = &mtl_dpll_funcs; in intel_dpll_init_clock_hook()
1554 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; in intel_dpll_init_clock_hook()
1556 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; in intel_dpll_init_clock_hook()
1558 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; in intel_dpll_init_clock_hook()
1560 dev_priv->display.funcs.dpll = &chv_dpll_funcs; in intel_dpll_init_clock_hook()
1562 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; in intel_dpll_init_clock_hook()
1564 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; in intel_dpll_init_clock_hook()
1566 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; in intel_dpll_init_clock_hook()
1568 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; in intel_dpll_init_clock_hook()
1570 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; in intel_dpll_init_clock_hook()
1585 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local
1600 * the P1/P2 dividers. Otherwise the DPLL will keep using the old in i9xx_enable_pll()
1603 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); in i9xx_enable_pll()
1604 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1607 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1615 * DPLL is enabled and the clocks are stable. in i9xx_enable_pll()
1619 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1624 intel_de_write(dev_priv, DPLL(pipe), dpll); in i9xx_enable_pll()
1625 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_enable_pll()
1670 bestn = crtc_state->dpll.n; in vlv_prepare_pll()
1671 bestm1 = crtc_state->dpll.m1; in vlv_prepare_pll()
1672 bestm2 = crtc_state->dpll.m2; in vlv_prepare_pll()
1673 bestp1 = crtc_state->dpll.p1; in vlv_prepare_pll()
1674 bestp2 = crtc_state->dpll.p2; in vlv_prepare_pll()
1755 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _vlv_enable_pll()
1756 intel_de_posting_read(dev_priv, DPLL(pipe)); in _vlv_enable_pll()
1759 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
1760 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); in _vlv_enable_pll()
1775 intel_de_write(dev_priv, DPLL(pipe), in vlv_enable_pll()
1776 crtc_state->dpll_hw_state.dpll & in vlv_enable_pll()
1779 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in vlv_enable_pll()
1800 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; in chv_prepare_pll()
1801 bestm2 = crtc_state->dpll.m2 >> 22; in chv_prepare_pll()
1802 bestp1 = crtc_state->dpll.p1; in chv_prepare_pll()
1803 bestp2 = crtc_state->dpll.p2; in chv_prepare_pll()
1804 vco = crtc_state->dpll.vco; in chv_prepare_pll()
1906 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); in _chv_enable_pll()
1909 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
1925 intel_de_write(dev_priv, DPLL(pipe), in chv_enable_pll()
1926 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); in chv_enable_pll()
1928 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { in chv_enable_pll()
1951 (intel_de_read(dev_priv, DPLL(PIPE_B)) & in chv_enable_pll()
1964 * @dpll: PLL configuration
1966 * Enable the PLL for @pipe using the supplied @dpll config. To be used
1971 const struct dpll *dpll) in vlv_force_pll_on() argument
1982 crtc_state->dpll = *dpll; in vlv_force_pll_on()
2010 intel_de_write(dev_priv, DPLL(pipe), val); in vlv_disable_pll()
2011 intel_de_posting_read(dev_priv, DPLL(pipe)); in vlv_disable_pll()
2027 intel_de_write(dev_priv, DPLL(pipe), val); in chv_disable_pll()
2028 intel_de_posting_read(dev_priv, DPLL(pipe)); in chv_disable_pll()
2053 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
2054 intel_de_posting_read(dev_priv, DPLL(pipe)); in i9xx_disable_pll()
2080 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in assert_pll()