41 #define lt_err(_intel_dp, _dp_phy, _format, ...) do { \  macro
792 		lt_err(intel_dp, dp_phy, "Failed to enable link training\n");  in intel_dp_link_training_clock_recovery()
815 			lt_err(intel_dp, dp_phy, "Failed to get link status\n");  in intel_dp_link_training_clock_recovery()
840 			lt_err(intel_dp, dp_phy, "Failed to update link training\n");  in intel_dp_link_training_clock_recovery()
856 	lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n",  in intel_dp_link_training_clock_recovery()
947 		lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n");  in intel_dp_link_training_channel_equalization()
956 			lt_err(intel_dp, dp_phy, "Failed to get link status\n");  in intel_dp_link_training_channel_equalization()
980 			lt_err(intel_dp, dp_phy, "Failed to update link training\n");  in intel_dp_link_training_channel_equalization()
1148 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n");  in intel_dp_128b132b_lane_eq()
1156 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n");  in intel_dp_128b132b_lane_eq()
1163 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n");  in intel_dp_128b132b_lane_eq()
1170 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n");  in intel_dp_128b132b_lane_eq()
1187 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");  in intel_dp_128b132b_lane_eq()
1193 			lt_err(intel_dp, DP_PHY_DPRX,  in intel_dp_128b132b_lane_eq()
1205 			lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n");  in intel_dp_128b132b_lane_eq()
1215 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n");  in intel_dp_128b132b_lane_eq()
1222 		lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n");  in intel_dp_128b132b_lane_eq()
1231 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");  in intel_dp_128b132b_lane_eq()
1237 			lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");  in intel_dp_128b132b_lane_eq()
1248 			lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n");  in intel_dp_128b132b_lane_eq()
1271 		lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n");  in intel_dp_128b132b_lane_cds()
1287 			lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n");  in intel_dp_128b132b_lane_cds()
1300 			lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n");  in intel_dp_128b132b_lane_cds()
1306 			lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n");  in intel_dp_128b132b_lane_cds()
1325 		lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n");  in intel_dp_128b132b_link_train()