36 #define lt_dbg(_intel_dp, _dp_phy, _format, ...) \  macro
47 		lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \
74 		lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n");  in intel_dp_read_lttpr_phy_caps()
78 	lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n",  in intel_dp_read_lttpr_phy_caps()
93 	lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n",  in intel_dp_read_lttpr_common_caps()
150 		lt_dbg(intel_dp, DP_PHY_DPRX,  in intel_dp_init_lttpr()
423 		lt_dbg(intel_dp, dp_phy,  in intel_dp_get_adjust_train()
429 		lt_dbg(intel_dp, dp_phy,  in intel_dp_get_adjust_train()
497 		lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n",  in intel_dp_program_link_training_pattern()
535 		lt_dbg(intel_dp, dp_phy,  in intel_dp_set_signal_levels()
541 		lt_dbg(intel_dp, dp_phy,  in intel_dp_set_signal_levels()
709 		lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n");  in intel_dp_prepare_link_train()
716 		lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n",  in intel_dp_prepare_link_train()
719 		lt_dbg(intel_dp, DP_PHY_DPRX,  in intel_dp_prepare_link_train()
763 	lt_dbg(intel_dp, dp_phy,  in intel_dp_dump_link_status()
820 			lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n");  in intel_dp_link_training_clock_recovery()
826 			lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n");  in intel_dp_link_training_clock_recovery()
832 			lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n");  in intel_dp_link_training_clock_recovery()
891 			lt_dbg(intel_dp, dp_phy,  in intel_dp_training_pattern()
894 			lt_dbg(intel_dp, dp_phy,  in intel_dp_training_pattern()
909 			lt_dbg(intel_dp, dp_phy,  in intel_dp_training_pattern()
912 			lt_dbg(intel_dp, dp_phy,  in intel_dp_training_pattern()
964 			lt_dbg(intel_dp, dp_phy,  in intel_dp_link_training_channel_equalization()
972 			lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n");  in intel_dp_link_training_channel_equalization()
988 		lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n");  in intel_dp_link_training_channel_equalization()
1012 		lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n");  in intel_dp_128b132b_intra_hop()
1046 		lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n");  in intel_dp_stop_link_train()
1066 	lt_dbg(intel_dp, dp_phy,  in intel_dp_link_train_phy()
1081 		lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n");  in intel_dp_schedule_fallback_link_training()
1086 		lt_dbg(intel_dp, DP_PHY_DPRX,  in intel_dp_schedule_fallback_link_training()
1199 			lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n");  in intel_dp_128b132b_lane_eq()
1242 			lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n");  in intel_dp_128b132b_lane_eq()
1294 			lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n");  in intel_dp_128b132b_lane_cds()
1333 	lt_dbg(intel_dp, DP_PHY_DPRX,  in intel_dp_128b132b_link_train()
1387 		lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n");  in intel_dp_start_link_train()
1410 	lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n");  in intel_dp_128b132b_sdp_crc16()