28 #define INTEL_CX0_LANE0		BIT(0)  macro
30 #define INTEL_CX0_BOTH_LANES	(INTEL_CX0_LANE1 | INTEL_CX0_LANE0)
1812 	u8 lane = INTEL_CX0_LANE0;  in intel_c10pll_readout_hw_state()
1857 		intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_PLL(i),  in intel_c10_pll_program()
1861 …intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE…  in intel_c10_pll_program()
1862 …intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_C…  in intel_c10_pll_program()
1864 	intel_cx0_rmw(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1),  in intel_c10_pll_program()
2072 …cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & PHY_…  in intel_c20pll_readout_hw_state()
2077 			pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20pll_readout_hw_state()
2080 			pll_state->tx[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20pll_readout_hw_state()
2087 			pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20pll_readout_hw_state()
2090 			pll_state->cmn[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20pll_readout_hw_state()
2098 				pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20pll_readout_hw_state()
2101 				pll_state->mpllb[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20pll_readout_hw_state()
2108 				pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20pll_readout_hw_state()
2111 				pll_state->mplla[i] = intel_c20_sram_read(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20pll_readout_hw_state()
2242 	int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0;  in intel_c20_pll_program()
2250 …cntx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(…  in intel_c20_pll_program()
2259 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(…  in intel_c20_pll_program()
2267 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx…  in intel_c20_pll_program()
2269 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx…  in intel_c20_pll_program()
2275 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->c…  in intel_c20_pll_program()
2277 …intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->c…  in intel_c20_pll_program()
2284 				intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2288 				intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2295 				intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2299 				intel_c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0,  in intel_c20_pll_program()
2540 				  INTEL_CX0_LANE0;  in intel_cx0_phy_lane_reset()
2569 						       INTEL_CX0_LANE0),  in intel_cx0_phy_lane_reset()
2575 								       INTEL_CX0_LANE0),  in intel_cx0_phy_lane_reset()
2608 	l0t1 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2));  in intel_cx0_program_phy_lane()
2609 	l0t2 = intel_cx0_read(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2));  in intel_cx0_program_phy_lane()
2659 	intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(1, 2),  in intel_cx0_program_phy_lane()
2661 	intel_cx0_write(i915, port, INTEL_CX0_LANE0, PHY_CX0_TX_CONTROL(2, 2),  in intel_cx0_program_phy_lane()
2705 					  INTEL_CX0_LANE0;  in intel_cx0pll_enable()