Lines Matching +full:0 +full:x84
25 for ((__lane) = 0; (__lane) < 2; (__lane)++) \
28 #define INTEL_CX0_LANE0 BIT(0)
44 return 0; in lane_mask_to_lane()
86 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET); in intel_clear_response_ready_flag()
117 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
124 drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), in intel_cx0_wait_for_ack()
131 drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), in intel_cx0_wait_for_ack()
137 return 0; in intel_cx0_wait_for_ack()
162 if (ack < 0) in __intel_cx0_read_once()
179 for (i = 0; i < 3; i++) { in __intel_cx0_read()
182 if (status >= 0) in __intel_cx0_read()
189 return 0; in __intel_cx0_read()
234 if (ack < 0) in __intel_cx0_write_once()
246 return 0; in __intel_cx0_write_once()
258 for (i = 0; i < 3; i++) { in __intel_cx0_write()
261 if (status == 0) in __intel_cx0_write()
283 intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_write()
284 intel_cx0_write(i915, port, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0); in intel_c20_sram_write()
286 intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_H, data >> 8, 0); in intel_c20_sram_write()
287 intel_cx0_write(i915, port, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); in intel_c20_sram_write()
297 intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_read()
298 intel_cx0_write(i915, port, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); in intel_c20_sram_read()
375 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
386 for (ln = 0; ln < crtc_state->lane_count; ln++) { in intel_cx0_phy_set_signal_levels()
393 intel_cx0_rmw(i915, encoder->port, BIT(lane), PHY_CX0_VDROVRD_CTL(lane, tx, 0), in intel_cx0_phy_set_signal_levels()
407 /* Write Override enables in 0xD71 */ in intel_cx0_phy_set_signal_levels()
409 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, in intel_cx0_phy_set_signal_levels()
414 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); in intel_cx0_phy_set_signal_levels()
422 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
423 * programmed 0.
428 .tx = 0x10,
429 .cmn = 0x21,
430 .pll[0] = 0xB4,
431 .pll[1] = 0,
432 .pll[2] = 0x30,
433 .pll[3] = 0x1,
434 .pll[4] = 0x26,
435 .pll[5] = 0x0C,
436 .pll[6] = 0x98,
437 .pll[7] = 0x46,
438 .pll[8] = 0x1,
439 .pll[9] = 0x1,
440 .pll[10] = 0,
441 .pll[11] = 0,
442 .pll[12] = 0xC0,
443 .pll[13] = 0,
444 .pll[14] = 0,
445 .pll[15] = 0x2,
446 .pll[16] = 0x84,
447 .pll[17] = 0x4F,
448 .pll[18] = 0xE5,
449 .pll[19] = 0x23,
454 .tx = 0x10,
455 .cmn = 0x21,
456 .pll[0] = 0x4,
457 .pll[1] = 0,
458 .pll[2] = 0xA2,
459 .pll[3] = 0x1,
460 .pll[4] = 0x33,
461 .pll[5] = 0x10,
462 .pll[6] = 0x75,
463 .pll[7] = 0xB3,
464 .pll[8] = 0x1,
465 .pll[9] = 0x1,
466 .pll[10] = 0,
467 .pll[11] = 0,
468 .pll[12] = 0,
469 .pll[13] = 0,
470 .pll[14] = 0,
471 .pll[15] = 0x2,
472 .pll[16] = 0x85,
473 .pll[17] = 0x0F,
474 .pll[18] = 0xE6,
475 .pll[19] = 0x23,
480 .tx = 0x10,
481 .cmn = 0x21,
482 .pll[0] = 0x34,
483 .pll[1] = 0,
484 .pll[2] = 0xDA,
485 .pll[3] = 0x1,
486 .pll[4] = 0x39,
487 .pll[5] = 0x12,
488 .pll[6] = 0xE3,
489 .pll[7] = 0xE9,
490 .pll[8] = 0x1,
491 .pll[9] = 0x1,
492 .pll[10] = 0,
493 .pll[11] = 0,
494 .pll[12] = 0x20,
495 .pll[13] = 0,
496 .pll[14] = 0,
497 .pll[15] = 0x2,
498 .pll[16] = 0x85,
499 .pll[17] = 0x8F,
500 .pll[18] = 0xE6,
501 .pll[19] = 0x23,
506 .tx = 0x10,
507 .cmn = 0x21,
508 .pll[0] = 0xF4,
509 .pll[1] = 0,
510 .pll[2] = 0xF8,
511 .pll[3] = 0x0,
512 .pll[4] = 0x20,
513 .pll[5] = 0x0A,
514 .pll[6] = 0x29,
515 .pll[7] = 0x10,
516 .pll[8] = 0x1, /* Verify */
517 .pll[9] = 0x1,
518 .pll[10] = 0,
519 .pll[11] = 0,
520 .pll[12] = 0xA0,
521 .pll[13] = 0,
522 .pll[14] = 0,
523 .pll[15] = 0x1,
524 .pll[16] = 0x84,
525 .pll[17] = 0x4F,
526 .pll[18] = 0xE5,
527 .pll[19] = 0x23,
532 .tx = 0x10,
533 .cmn = 0x21,
534 .pll[0] = 0xB4,
535 .pll[1] = 0,
536 .pll[2] = 0x30,
537 .pll[3] = 0x1,
538 .pll[4] = 0x26,
539 .pll[5] = 0x0C,
540 .pll[6] = 0x98,
541 .pll[7] = 0x46,
542 .pll[8] = 0x1,
543 .pll[9] = 0x1,
544 .pll[10] = 0,
545 .pll[11] = 0,
546 .pll[12] = 0xC0,
547 .pll[13] = 0,
548 .pll[14] = 0,
549 .pll[15] = 0x1,
550 .pll[16] = 0x85,
551 .pll[17] = 0x4F,
552 .pll[18] = 0xE6,
553 .pll[19] = 0x23,
558 .tx = 0x10,
559 .cmn = 0x21,
560 .pll[0] = 0x4,
561 .pll[1] = 0,
562 .pll[2] = 0xA2,
563 .pll[3] = 0x1,
564 .pll[4] = 0x33,
565 .pll[5] = 0x10,
566 .pll[6] = 0x75,
567 .pll[7] = 0xB3,
568 .pll[8] = 0x1,
569 .pll[9] = 0x1,
570 .pll[10] = 0,
571 .pll[11] = 0,
572 .pll[12] = 0,
573 .pll[13] = 0,
574 .pll[14] = 0,
575 .pll[15] = 0x1,
576 .pll[16] = 0x85,
577 .pll[17] = 0x0F,
578 .pll[18] = 0xE6,
579 .pll[19] = 0x23,
584 .tx = 0x10,
585 .cmn = 0x21,
586 .pll[0] = 0xF4,
587 .pll[1] = 0,
588 .pll[2] = 0xF8,
589 .pll[3] = 0,
590 .pll[4] = 0x20,
591 .pll[5] = 0x0A,
592 .pll[6] = 0x29,
593 .pll[7] = 0x10,
594 .pll[8] = 0x1,
595 .pll[9] = 0x1,
596 .pll[10] = 0,
597 .pll[11] = 0,
598 .pll[12] = 0xA0,
599 .pll[13] = 0,
600 .pll[14] = 0,
601 .pll[15] = 0,
602 .pll[16] = 0x84,
603 .pll[17] = 0x4F,
604 .pll[18] = 0xE5,
605 .pll[19] = 0x23,
610 .tx = 0x10,
611 .cmn = 0x21,
612 .pll[0] = 0xB4,
613 .pll[1] = 0,
614 .pll[2] = 0x3E,
615 .pll[3] = 0x1,
616 .pll[4] = 0xA8,
617 .pll[5] = 0x0C,
618 .pll[6] = 0x33,
619 .pll[7] = 0x54,
620 .pll[8] = 0x1,
621 .pll[9] = 0x1,
622 .pll[10] = 0,
623 .pll[11] = 0,
624 .pll[12] = 0xC8,
625 .pll[13] = 0,
626 .pll[14] = 0,
627 .pll[15] = 0,
628 .pll[16] = 0x85,
629 .pll[17] = 0x8F,
630 .pll[18] = 0xE6,
631 .pll[19] = 0x23,
636 .tx = 0x10,
637 .cmn = 0x21,
638 .pll[0] = 0x34,
639 .pll[1] = 0,
640 .pll[2] = 0x84,
641 .pll[3] = 0x1,
642 .pll[4] = 0x30,
643 .pll[5] = 0x0F,
644 .pll[6] = 0x3D,
645 .pll[7] = 0x98,
646 .pll[8] = 0x1,
647 .pll[9] = 0x1,
648 .pll[10] = 0,
649 .pll[11] = 0,
650 .pll[12] = 0xF0,
651 .pll[13] = 0,
652 .pll[14] = 0,
653 .pll[15] = 0,
654 .pll[16] = 0x84,
655 .pll[17] = 0x0F,
656 .pll[18] = 0xE5,
657 .pll[19] = 0x23,
685 .tx = { 0xbe88, /* tx cfg0 */
686 0x5800, /* tx cfg1 */
687 0x0000, /* tx cfg2 */
689 .cmn = {0x0500, /* cmn cfg0*/
690 0x0005, /* cmn cfg1 */
691 0x0000, /* cmn cfg2 */
692 0x0000, /* cmn cfg3 */
694 .mpllb = { 0x50a8, /* mpllb cfg0 */
695 0x2120, /* mpllb cfg1 */
696 0xcd9a, /* mpllb cfg2 */
697 0xbfc1, /* mpllb cfg3 */
698 0x5ab8, /* mpllb cfg4 */
699 0x4c34, /* mpllb cfg5 */
700 0x2000, /* mpllb cfg6 */
701 0x0001, /* mpllb cfg7 */
702 0x6000, /* mpllb cfg8 */
703 0x0000, /* mpllb cfg9 */
704 0x0000, /* mpllb cfg10 */
711 .tx = { 0xbe88, /* tx cfg0 */
712 0x4800, /* tx cfg1 */
713 0x0000, /* tx cfg2 */
715 .cmn = {0x0500, /* cmn cfg0*/
716 0x0005, /* cmn cfg1 */
717 0x0000, /* cmn cfg2 */
718 0x0000, /* cmn cfg3 */
720 .mpllb = { 0x308c, /* mpllb cfg0 */
721 0x2110, /* mpllb cfg1 */
722 0xcc9c, /* mpllb cfg2 */
723 0xbfc1, /* mpllb cfg3 */
724 0x4b9a, /* mpllb cfg4 */
725 0x3f81, /* mpllb cfg5 */
726 0x2000, /* mpllb cfg6 */
727 0x0001, /* mpllb cfg7 */
728 0x5000, /* mpllb cfg8 */
729 0x0000, /* mpllb cfg9 */
730 0x0000, /* mpllb cfg10 */
737 .tx = { 0xbe88, /* tx cfg0 */
738 0x4800, /* tx cfg1 */
739 0x0000, /* tx cfg2 */
741 .cmn = {0x0500, /* cmn cfg0*/
742 0x0005, /* cmn cfg1 */
743 0x0000, /* cmn cfg2 */
744 0x0000, /* cmn cfg3 */
746 .mpllb = { 0x108c, /* mpllb cfg0 */
747 0x2108, /* mpllb cfg1 */
748 0xcc9c, /* mpllb cfg2 */
749 0xbfc1, /* mpllb cfg3 */
750 0x4b9a, /* mpllb cfg4 */
751 0x3f81, /* mpllb cfg5 */
752 0x2000, /* mpllb cfg6 */
753 0x0001, /* mpllb cfg7 */
754 0x5000, /* mpllb cfg8 */
755 0x0000, /* mpllb cfg9 */
756 0x0000, /* mpllb cfg10 */
763 .tx = { 0xbe88, /* tx cfg0 */
764 0x4800, /* tx cfg1 */
765 0x0000, /* tx cfg2 */
767 .cmn = {0x0500, /* cmn cfg0*/
768 0x0005, /* cmn cfg1 */
769 0x0000, /* cmn cfg2 */
770 0x0000, /* cmn cfg3 */
772 .mpllb = { 0x10d2, /* mpllb cfg0 */
773 0x2108, /* mpllb cfg1 */
774 0x8d98, /* mpllb cfg2 */
775 0xbfc1, /* mpllb cfg3 */
776 0x7166, /* mpllb cfg4 */
777 0x5f42, /* mpllb cfg5 */
778 0x2000, /* mpllb cfg6 */
779 0x0001, /* mpllb cfg7 */
780 0x7800, /* mpllb cfg8 */
781 0x0000, /* mpllb cfg9 */
782 0x0000, /* mpllb cfg10 */
790 .tx = { 0xbe21, /* tx cfg0 */
791 0x4800, /* tx cfg1 */
792 0x0000, /* tx cfg2 */
794 .cmn = {0x0500, /* cmn cfg0*/
795 0x0005, /* cmn cfg1 */
796 0x0000, /* cmn cfg2 */
797 0x0000, /* cmn cfg3 */
799 .mplla = { 0x3104, /* mplla cfg0 */
800 0xd105, /* mplla cfg1 */
801 0xc025, /* mplla cfg2 */
802 0xc025, /* mplla cfg3 */
803 0x8c00, /* mplla cfg4 */
804 0x759a, /* mplla cfg5 */
805 0x4000, /* mplla cfg6 */
806 0x0003, /* mplla cfg7 */
807 0x3555, /* mplla cfg8 */
808 0x0001, /* mplla cfg9 */
815 .tx = { 0xbea0, /* tx cfg0 */
816 0x4800, /* tx cfg1 */
817 0x0000, /* tx cfg2 */
819 .cmn = {0x0500, /* cmn cfg0*/
820 0x0005, /* cmn cfg1 */
821 0x0000, /* cmn cfg2 */
822 0x0000, /* cmn cfg3 */
824 .mpllb = { 0x015f, /* mpllb cfg0 */
825 0x2205, /* mpllb cfg1 */
826 0x1b17, /* mpllb cfg2 */
827 0xffc1, /* mpllb cfg3 */
828 0xe100, /* mpllb cfg4 */
829 0xbd00, /* mpllb cfg5 */
830 0x2000, /* mpllb cfg6 */
831 0x0001, /* mpllb cfg7 */
832 0x4800, /* mpllb cfg8 */
833 0x0000, /* mpllb cfg9 */
834 0x0000, /* mpllb cfg10 */
841 .tx = { 0xbe20, /* tx cfg0 */
842 0x4800, /* tx cfg1 */
843 0x0000, /* tx cfg2 */
845 .cmn = {0x0500, /* cmn cfg0*/
846 0x0005, /* cmn cfg1 */
847 0x0000, /* cmn cfg2 */
848 0x0000, /* cmn cfg3 */
850 .mplla = { 0x3104, /* mplla cfg0 */
851 0xd105, /* mplla cfg1 */
852 0xc025, /* mplla cfg2 */
853 0xc025, /* mplla cfg3 */
854 0xa6ab, /* mplla cfg4 */
855 0x8c00, /* mplla cfg5 */
856 0x4000, /* mplla cfg6 */
857 0x0003, /* mplla cfg7 */
858 0x3555, /* mplla cfg8 */
859 0x0001, /* mplla cfg9 */
880 .tx = 0x10,
881 .cmn = 0x1,
882 .pll[0] = 0x4,
883 .pll[1] = 0,
884 .pll[2] = 0xB2,
885 .pll[3] = 0,
886 .pll[4] = 0,
887 .pll[5] = 0,
888 .pll[6] = 0,
889 .pll[7] = 0,
890 .pll[8] = 0x20,
891 .pll[9] = 0x1,
892 .pll[10] = 0,
893 .pll[11] = 0,
894 .pll[12] = 0,
895 .pll[13] = 0,
896 .pll[14] = 0,
897 .pll[15] = 0xD,
898 .pll[16] = 0x6,
899 .pll[17] = 0x8F,
900 .pll[18] = 0x84,
901 .pll[19] = 0x23,
906 .tx = 0x10,
907 .cmn = 0x1,
908 .pll[0] = 0x34,
909 .pll[1] = 0,
910 .pll[2] = 0xC0,
911 .pll[3] = 0,
912 .pll[4] = 0,
913 .pll[5] = 0,
914 .pll[6] = 0,
915 .pll[7] = 0,
916 .pll[8] = 0x20,
917 .pll[9] = 0x1,
918 .pll[10] = 0,
919 .pll[11] = 0,
920 .pll[12] = 0x80,
921 .pll[13] = 0,
922 .pll[14] = 0,
923 .pll[15] = 0xD,
924 .pll[16] = 0x6,
925 .pll[17] = 0xCF,
926 .pll[18] = 0x84,
927 .pll[19] = 0x23,
932 .tx = 0x10,
933 .cmn = 0x1,
934 .pll[0] = 0xF4,
935 .pll[1] = 0,
936 .pll[2] = 0x7A,
937 .pll[3] = 0,
938 .pll[4] = 0,
939 .pll[5] = 0,
940 .pll[6] = 0,
941 .pll[7] = 0,
942 .pll[8] = 0x20,
943 .pll[9] = 0x1,
944 .pll[10] = 0,
945 .pll[11] = 0,
946 .pll[12] = 0x58,
947 .pll[13] = 0,
948 .pll[14] = 0,
949 .pll[15] = 0xB,
950 .pll[16] = 0x6,
951 .pll[17] = 0xF,
952 .pll[18] = 0x85,
953 .pll[19] = 0x23,
958 .tx = 0x10,
959 .cmn = 0x1,
960 .pll[0] = 0xF4,
961 .pll[1] = 0,
962 .pll[2] = 0x7A,
963 .pll[3] = 0,
964 .pll[4] = 0,
965 .pll[5] = 0,
966 .pll[6] = 0,
967 .pll[7] = 0,
968 .pll[8] = 0x20,
969 .pll[9] = 0x1,
970 .pll[10] = 0,
971 .pll[11] = 0,
972 .pll[12] = 0x58,
973 .pll[13] = 0,
974 .pll[14] = 0,
975 .pll[15] = 0xA,
976 .pll[16] = 0x6,
977 .pll[17] = 0xF,
978 .pll[18] = 0x85,
979 .pll[19] = 0x23,
984 .tx = 0x10,
985 .cmn = 0x1,
986 .pll[0] = 0xF4,
987 .pll[1] = 0,
988 .pll[2] = 0x7A,
989 .pll[3] = 0,
990 .pll[4] = 0,
991 .pll[5] = 0,
992 .pll[6] = 0,
993 .pll[7] = 0,
994 .pll[8] = 0x20,
995 .pll[9] = 0x1,
996 .pll[10] = 0,
997 .pll[11] = 0,
998 .pll[12] = 0x58,
999 .pll[13] = 0,
1000 .pll[14] = 0,
1001 .pll[15] = 0x8,
1002 .pll[16] = 0x6,
1003 .pll[17] = 0xF,
1004 .pll[18] = 0x85,
1005 .pll[19] = 0x23,
1011 .tx = 0x10,
1012 .cmn = 0x1,
1013 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1014 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1015 .pll[10] = 0xFF, .pll[11] = 0xCC, .pll[12] = 0x9C, .pll[13] = 0xCB, .pll[14] = 0xCC,
1016 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1021 .tx = 0x10,
1022 .cmn = 0x1,
1023 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1024 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1025 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1026 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1031 .tx = 0x10,
1032 .cmn = 0x1,
1033 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1034 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1035 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1036 .pll[15] = 0x0D, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1041 .tx = 0x10,
1042 .cmn = 0x1,
1043 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1044 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1045 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xA0, .pll[13] = 0x00, .pll[14] = 0x00,
1046 .pll[15] = 0x0C, .pll[16] = 0x09, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1051 .tx = 0x10,
1052 .cmn = 0x1,
1053 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1054 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1055 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x00, .pll[13] = 0x00, .pll[14] = 0x00,
1056 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1061 .tx = 0x10,
1062 .cmn = 0x1,
1063 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1064 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1065 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x55, .pll[13] = 0x55, .pll[14] = 0x55,
1066 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1071 .tx = 0x10,
1072 .cmn = 0x1,
1073 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1074 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1075 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1076 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1081 .tx = 0x10,
1082 .cmn = 0x1,
1083 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1084 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1085 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x2A, .pll[13] = 0xA9, .pll[14] = 0xAA,
1086 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1091 .tx = 0x10,
1092 .cmn = 0x1,
1093 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1094 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1095 .pll[10] = 0xFF, .pll[11] = 0x77, .pll[12] = 0x57, .pll[13] = 0x77, .pll[14] = 0x77,
1096 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1101 .tx = 0x10,
1102 .cmn = 0x1,
1103 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1104 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1105 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xD5, .pll[13] = 0x55, .pll[14] = 0x55,
1106 .pll[15] = 0x0C, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1111 .tx = 0x10,
1112 .cmn = 0x1,
1113 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1114 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1115 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xB5, .pll[13] = 0x55, .pll[14] = 0x55,
1116 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1121 .tx = 0x10,
1122 .cmn = 0x1,
1123 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1124 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1125 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1126 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1131 .tx = 0x10,
1132 .cmn = 0x1,
1133 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1134 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1135 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1136 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1141 .tx = 0x10,
1142 .cmn = 0x1,
1143 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1144 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1145 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1146 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1151 .tx = 0x10,
1152 .cmn = 0x1,
1153 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1154 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1155 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x08, .pll[13] = 0x00, .pll[14] = 0x00,
1156 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1161 .tx = 0x10,
1162 .cmn = 0x1,
1163 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1164 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1165 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x10, .pll[13] = 0x00, .pll[14] = 0x00,
1166 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1171 .tx = 0x10,
1172 .cmn = 0x1,
1173 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1174 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1175 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x72, .pll[13] = 0xA9, .pll[14] = 0xAA,
1176 .pll[15] = 0x0B, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1181 .tx = 0x10,
1182 .cmn = 0x1,
1183 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1184 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1185 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xF0, .pll[13] = 0x00, .pll[14] = 0x00,
1186 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1191 .tx = 0x10,
1192 .cmn = 0x1,
1193 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1194 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1195 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x80, .pll[13] = 0x00, .pll[14] = 0x00,
1196 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1201 .tx = 0x10,
1202 .cmn = 0x1,
1203 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1204 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1205 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1206 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1211 .tx = 0x10,
1212 .cmn = 0x1,
1213 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1214 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1215 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xF5, .pll[13] = 0x55, .pll[14] = 0x55,
1216 .pll[15] = 0x0B, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1221 .tx = 0x10,
1222 .cmn = 0x1,
1223 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1224 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1225 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x50, .pll[13] = 0x00, .pll[14] = 0x00,
1226 .pll[15] = 0x0A, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1231 .tx = 0x10,
1232 .cmn = 0x1,
1233 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1234 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1235 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x22, .pll[13] = 0xA9, .pll[14] = 0xAA,
1236 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1241 .tx = 0x10,
1242 .cmn = 0x1,
1243 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1244 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1245 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0xA5, .pll[13] = 0x55, .pll[14] = 0x55,
1246 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1251 .tx = 0x10,
1252 .cmn = 0x1,
1253 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1254 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1255 .pll[10] = 0xFF, .pll[11] = 0x44, .pll[12] = 0x44, .pll[13] = 0x44, .pll[14] = 0x44,
1256 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1261 .tx = 0x10,
1262 .cmn = 0x1,
1263 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1264 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1265 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x35, .pll[13] = 0x55, .pll[14] = 0x55,
1266 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1271 .tx = 0x10,
1272 .cmn = 0x1,
1273 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1274 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1275 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x60, .pll[13] = 0x00, .pll[14] = 0x00,
1276 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1281 .tx = 0x10,
1282 .cmn = 0x1,
1283 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1284 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1285 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0xFA, .pll[13] = 0xA9, .pll[14] = 0xAA,
1286 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1291 .tx = 0x10,
1292 .cmn = 0x1,
1293 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1294 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1295 .pll[10] = 0xFF, .pll[11] = 0x99, .pll[12] = 0x05, .pll[13] = 0x98, .pll[14] = 0x99,
1296 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1301 .tx = 0x10,
1302 .cmn = 0x1,
1303 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1304 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1305 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x20, .pll[13] = 0x00, .pll[14] = 0x00,
1306 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1311 .tx = 0x10,
1312 .cmn = 0x1,
1313 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1314 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1315 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x45, .pll[13] = 0x55, .pll[14] = 0x55,
1316 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1321 .tx = 0x10,
1322 .cmn = 0x1,
1323 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1324 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1325 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xC8, .pll[13] = 0x00, .pll[14] = 0x00,
1326 .pll[15] = 0x0A, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1331 .tx = 0x10,
1332 .cmn = 0x1,
1333 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1334 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1335 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x6C, .pll[13] = 0xA9, .pll[14] = 0xAA,
1336 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1341 .tx = 0x10,
1342 .cmn = 0x1,
1343 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1344 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1345 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0xEC, .pll[13] = 0x00, .pll[14] = 0x00,
1346 .pll[15] = 0x09, .pll[16] = 0x09, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1351 .tx = 0x10,
1352 .cmn = 0x1,
1353 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1354 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1355 .pll[10] = 0xFF, .pll[11] = 0x33, .pll[12] = 0x44, .pll[13] = 0x33, .pll[14] = 0x33,
1356 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1361 .tx = 0x10,
1362 .cmn = 0x1,
1363 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1364 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1365 .pll[10] = 0xFF, .pll[11] = 0x00, .pll[12] = 0x58, .pll[13] = 0x00, .pll[14] = 0x00,
1366 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1371 .tx = 0x10,
1372 .cmn = 0x1,
1373 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1374 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1375 .pll[10] = 0xFF, .pll[11] = 0xAA, .pll[12] = 0x44, .pll[13] = 0xA9, .pll[14] = 0xAA,
1376 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1381 .tx = 0x10,
1382 .cmn = 0x1,
1383 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1384 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1385 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x9F, .pll[13] = 0x55, .pll[14] = 0x55,
1386 .pll[15] = 0x09, .pll[16] = 0x08, .pll[17] = 0xCF, .pll[18] = 0x84, .pll[19] = 0x23,
1391 .tx = 0x10,
1392 .cmn = 0x1,
1393 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1394 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1395 .pll[10] = 0xFF, .pll[11] = 0x55, .pll[12] = 0x15, .pll[13] = 0x55, .pll[14] = 0x55,
1396 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1401 .tx = 0x10,
1402 .cmn = 0x1,
1403 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1404 .pll[5] = 0x00, .pll[6] = 0x00, .pll[7] = 0x00, .pll[8] = 0x20, .pll[9] = 0xFF,
1405 .pll[10] = 0xFF, .pll[11] = 0x3B, .pll[12] = 0x44, .pll[13] = 0xBA, .pll[14] = 0xBB,
1406 .pll[15] = 0x08, .pll[16] = 0x08, .pll[17] = 0x8F, .pll[18] = 0x84, .pll[19] = 0x23,
1461 .tx = { 0xbe88, /* tx cfg0 */
1462 0x9800, /* tx cfg1 */
1463 0x0000, /* tx cfg2 */
1465 .cmn = { 0x0500, /* cmn cfg0*/
1466 0x0005, /* cmn cfg1 */
1467 0x0000, /* cmn cfg2 */
1468 0x0000, /* cmn cfg3 */
1470 .mpllb = { 0xa0d2, /* mpllb cfg0 */
1471 0x7d80, /* mpllb cfg1 */
1472 0x0906, /* mpllb cfg2 */
1473 0xbe40, /* mpllb cfg3 */
1474 0x0000, /* mpllb cfg4 */
1475 0x0000, /* mpllb cfg5 */
1476 0x0200, /* mpllb cfg6 */
1477 0x0001, /* mpllb cfg7 */
1478 0x0000, /* mpllb cfg8 */
1479 0x0000, /* mpllb cfg9 */
1480 0x0001, /* mpllb cfg10 */
1487 .tx = { 0xbe88, /* tx cfg0 */
1488 0x9800, /* tx cfg1 */
1489 0x0000, /* tx cfg2 */
1491 .cmn = { 0x0500, /* cmn cfg0*/
1492 0x0005, /* cmn cfg1 */
1493 0x0000, /* cmn cfg2 */
1494 0x0000, /* cmn cfg3 */
1496 .mpllb = { 0xa0e0, /* mpllb cfg0 */
1497 0x7d80, /* mpllb cfg1 */
1498 0x0906, /* mpllb cfg2 */
1499 0xbe40, /* mpllb cfg3 */
1500 0x0000, /* mpllb cfg4 */
1501 0x0000, /* mpllb cfg5 */
1502 0x2200, /* mpllb cfg6 */
1503 0x0001, /* mpllb cfg7 */
1504 0x8000, /* mpllb cfg8 */
1505 0x0000, /* mpllb cfg9 */
1506 0x0001, /* mpllb cfg10 */
1513 .tx = { 0xbe88, /* tx cfg0 */
1514 0x9800, /* tx cfg1 */
1515 0x0000, /* tx cfg2 */
1517 .cmn = { 0x0500, /* cmn cfg0*/
1518 0x0005, /* cmn cfg1 */
1519 0x0000, /* cmn cfg2 */
1520 0x0000, /* cmn cfg3 */
1522 .mpllb = { 0x609a, /* mpllb cfg0 */
1523 0x7d40, /* mpllb cfg1 */
1524 0xca06, /* mpllb cfg2 */
1525 0xbe40, /* mpllb cfg3 */
1526 0x0000, /* mpllb cfg4 */
1527 0x0000, /* mpllb cfg5 */
1528 0x2200, /* mpllb cfg6 */
1529 0x0001, /* mpllb cfg7 */
1530 0x5800, /* mpllb cfg8 */
1531 0x0000, /* mpllb cfg9 */
1532 0x0001, /* mpllb cfg10 */
1539 .tx = { 0xbe88, /* tx cfg0 */
1540 0x9800, /* tx cfg1 */
1541 0x0000, /* tx cfg2 */
1543 .cmn = { 0x0500, /* cmn cfg0*/
1544 0x0005, /* cmn cfg1 */
1545 0x0000, /* cmn cfg2 */
1546 0x0000, /* cmn cfg3 */
1548 .mpllb = { 0x409a, /* mpllb cfg0 */
1549 0x7d20, /* mpllb cfg1 */
1550 0xca06, /* mpllb cfg2 */
1551 0xbe40, /* mpllb cfg3 */
1552 0x0000, /* mpllb cfg4 */
1553 0x0000, /* mpllb cfg5 */
1554 0x2200, /* mpllb cfg6 */
1555 0x0001, /* mpllb cfg7 */
1556 0x5800, /* mpllb cfg8 */
1557 0x0000, /* mpllb cfg9 */
1558 0x0001, /* mpllb cfg10 */
1565 .tx = { 0xbe88, /* tx cfg0 */
1566 0x9800, /* tx cfg1 */
1567 0x0000, /* tx cfg2 */
1569 .cmn = { 0x0500, /* cmn cfg0*/
1570 0x0005, /* cmn cfg1 */
1571 0x0000, /* cmn cfg2 */
1572 0x0000, /* cmn cfg3 */
1574 .mpllb = { 0x009a, /* mpllb cfg0 */
1575 0x7d08, /* mpllb cfg1 */
1576 0xca06, /* mpllb cfg2 */
1577 0xbe40, /* mpllb cfg3 */
1578 0x0000, /* mpllb cfg4 */
1579 0x0000, /* mpllb cfg5 */
1580 0x2200, /* mpllb cfg6 */
1581 0x0001, /* mpllb cfg7 */
1582 0x5800, /* mpllb cfg8 */
1583 0x0000, /* mpllb cfg9 */
1584 0x0001, /* mpllb cfg10 */
1591 .tx = { 0xbe98, /* tx cfg0 */
1592 0x9800, /* tx cfg1 */
1593 0x0000, /* tx cfg2 */
1595 .cmn = { 0x0500, /* cmn cfg0*/
1596 0x0005, /* cmn cfg1 */
1597 0x0000, /* cmn cfg2 */
1598 0x0000, /* cmn cfg3 */
1600 .mpllb = { 0x209c, /* mpllb cfg0 */
1601 0x7d10, /* mpllb cfg1 */
1602 0xca06, /* mpllb cfg2 */
1603 0xbe40, /* mpllb cfg3 */
1604 0x0000, /* mpllb cfg4 */
1605 0x0000, /* mpllb cfg5 */
1606 0x2200, /* mpllb cfg6 */
1607 0x0001, /* mpllb cfg7 */
1608 0x2000, /* mpllb cfg8 */
1609 0x0000, /* mpllb cfg9 */
1610 0x0004, /* mpllb cfg10 */
1617 .tx = { 0xbe98, /* tx cfg0 */
1618 0x9800, /* tx cfg1 */
1619 0x0000, /* tx cfg2 */
1621 .cmn = { 0x0500, /* cmn cfg0*/
1622 0x0005, /* cmn cfg1 */
1623 0x0000, /* cmn cfg2 */
1624 0x0000, /* cmn cfg3 */
1626 .mpllb = { 0x009c, /* mpllb cfg0 */
1627 0x7d08, /* mpllb cfg1 */
1628 0xca06, /* mpllb cfg2 */
1629 0xbe40, /* mpllb cfg3 */
1630 0x0000, /* mpllb cfg4 */
1631 0x0000, /* mpllb cfg5 */
1632 0x2200, /* mpllb cfg6 */
1633 0x0001, /* mpllb cfg7 */
1634 0x2000, /* mpllb cfg8 */
1635 0x0000, /* mpllb cfg9 */
1636 0x0004, /* mpllb cfg10 */
1643 .tx = { 0xbe98, /* tx cfg0 */
1644 0x9800, /* tx cfg1 */
1645 0x0000, /* tx cfg2 */
1647 .cmn = { 0x0500, /* cmn cfg0*/
1648 0x0005, /* cmn cfg1 */
1649 0x0000, /* cmn cfg2 */
1650 0x0000, /* cmn cfg3 */
1652 .mpllb = { 0x00d0, /* mpllb cfg0 */
1653 0x7d08, /* mpllb cfg1 */
1654 0x4a06, /* mpllb cfg2 */
1655 0xbe40, /* mpllb cfg3 */
1656 0x0000, /* mpllb cfg4 */
1657 0x0000, /* mpllb cfg5 */
1658 0x2200, /* mpllb cfg6 */
1659 0x0003, /* mpllb cfg7 */
1660 0x2aaa, /* mpllb cfg8 */
1661 0x0002, /* mpllb cfg9 */
1662 0x0004, /* mpllb cfg10 */
1669 .tx = { 0xbe98, /* tx cfg0 */
1670 0x9800, /* tx cfg1 */
1671 0x0000, /* tx cfg2 */
1673 .cmn = { 0x0500, /* cmn cfg0*/
1674 0x0005, /* cmn cfg1 */
1675 0x0000, /* cmn cfg2 */
1676 0x0000, /* cmn cfg3 */
1678 .mpllb = { 0x1104, /* mpllb cfg0 */
1679 0x7d08, /* mpllb cfg1 */
1680 0x0a06, /* mpllb cfg2 */
1681 0xbe40, /* mpllb cfg3 */
1682 0x0000, /* mpllb cfg4 */
1683 0x0000, /* mpllb cfg5 */
1684 0x2200, /* mpllb cfg6 */
1685 0x0003, /* mpllb cfg7 */
1686 0x3555, /* mpllb cfg8 */
1687 0x0001, /* mpllb cfg9 */
1688 0x0004, /* mpllb cfg10 */
1695 .tx = { 0xbe98, /* tx cfg0 */
1696 0x9800, /* tx cfg1 */
1697 0x0000, /* tx cfg2 */
1699 .cmn = { 0x0500, /* cmn cfg0*/
1700 0x0005, /* cmn cfg1 */
1701 0x0000, /* cmn cfg2 */
1702 0x0000, /* cmn cfg3 */
1704 .mpllb = { 0x0138, /* mpllb cfg0 */
1705 0x7d08, /* mpllb cfg1 */
1706 0x5486, /* mpllb cfg2 */
1707 0xfe40, /* mpllb cfg3 */
1708 0x0000, /* mpllb cfg4 */
1709 0x0000, /* mpllb cfg5 */
1710 0x2200, /* mpllb cfg6 */
1711 0x0001, /* mpllb cfg7 */
1712 0x4000, /* mpllb cfg8 */
1713 0x0000, /* mpllb cfg9 */
1714 0x0004, /* mpllb cfg10 */
1737 for (i = 0; tables[i]; i++) { in intel_c10_phy_check_hdmi_link_rate()
1783 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
1796 for (i = 0; tables[i]; i++) { in intel_c10pll_calc_state()
1801 return 0; in intel_c10pll_calc_state()
1823 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10pll_readout_hw_state()
1826 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
1830 pll_state->cmn = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
1831 pll_state->tx = intel_cx0_read(i915, encoder->port, lane, PHY_C10_VDR_TX(0)); in intel_c10pll_readout_hw_state()
1844 0, C10_VDR_CTRL_MSGBUS_ACCESS, in intel_c10_pll_program()
1847 /* Custom width needs to be programmed to 0 for both the phy lanes */ in intel_c10_pll_program()
1852 0, C10_VDR_CTRL_UPDATE_CFG, in intel_c10_pll_program()
1856 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10_pll_program()
1861 …intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE… in intel_c10_pll_program()
1862 …intel_cx0_write(i915, encoder->port, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_C… in intel_c10_pll_program()
1865 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, in intel_c10_pll_program()
1874 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_dump_hw_state()
1877 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; in intel_c10pll_dump_hw_state()
1896 drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn); in intel_c10pll_dump_hw_state()
1899 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) in intel_c10pll_dump_hw_state()
1900 drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", in intel_c10pll_dump_hw_state()
1928 mpll_fracn_quot = (multiplier >> 16) & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
1929 mpll_fracn_rem = multiplier & 0xFFFF; in intel_c20_compute_hdmi_tmds_pll()
1945 pll_state->tx[0] = 0xbe88; in intel_c20_compute_hdmi_tmds_pll()
1946 pll_state->tx[1] = 0x9800; in intel_c20_compute_hdmi_tmds_pll()
1947 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1948 pll_state->cmn[0] = 0x0500; in intel_c20_compute_hdmi_tmds_pll()
1949 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
1950 pll_state->cmn[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1951 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1952 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | in intel_c20_compute_hdmi_tmds_pll()
1963 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1964 pll_state->mpllb[5] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
1971 return 0; in intel_c20_compute_hdmi_tmds_pll()
1979 for (i = 0; tables[i]; i++) { in intel_c20_phy_check_hdmi_link_rate()
2023 &crtc_state->cx0pll_state.c20) == 0) in intel_c20pll_calc_state()
2024 return 0; in intel_c20pll_calc_state()
2031 for (i = 0; tables[i]; i++) { in intel_c20pll_calc_state()
2034 return 0; in intel_c20pll_calc_state()
2075 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20pll_readout_hw_state()
2085 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20pll_readout_hw_state()
2094 if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { in intel_c20pll_readout_hw_state()
2096 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20pll_readout_hw_state()
2106 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20pll_readout_hw_state()
2125 drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2126 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2127 drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2128 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2131 for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) in intel_c20pll_dump_hw_state()
2132 drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); in intel_c20pll_dump_hw_state()
2134 for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) in intel_c20pll_dump_hw_state()
2135 drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); in intel_c20pll_dump_hw_state()
2143 return 0; in intel_c20_get_dp_rate()
2158 case 312500: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2160 case 421875: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2162 case 625000: /* 20 Gbps DP2.0*/ in intel_c20_get_dp_rate()
2170 return 0; in intel_c20_get_dp_rate()
2177 return 0; in intel_c20_get_hdmi_rate()
2190 return 0; in intel_c20_get_hdmi_rate()
2196 /* DP2.0 clock rates */ in is_dp2()
2233 return 0; in intel_get_c20_custom_width()
2250 …tx = intel_cx0_read(i915, encoder->port, INTEL_CX0_LANE0, PHY_C20_VDR_CUSTOM_SERDES_RATE) & BIT(0); in intel_c20_pll_program()
2254 * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA. in intel_c20_pll_program()
2258 for (i = 0; i < 4; i++) in intel_c20_pll_program()
2259 …c20_sram_write(i915, encoder->port, INTEL_CX0_LANE0, RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(i), 0); in intel_c20_pll_program()
2265 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20_pll_program()
2273 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20_pll_program()
2282 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20_pll_program()
2293 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20_pll_program()
2320 is_hdmi_frl(pll_state->clock) ? BIT(7) : 0, in intel_c20_pll_program()
2333 BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); in intel_c20_pll_program()
2339 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1; in intel_c10pll_calc_port_clock()
2341 int tmpclk = 0; in intel_c10pll_calc_port_clock()
2343 if (pll_state->pll[0] & C10_PLL0_FRACEN) { in intel_c10pll_calc_port_clock()
2373 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2375 if (pll_state->tx[0] & C20_PHY_USE_MPLLB) { in intel_c20pll_calc_port_clock()
2381 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2382 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2384 fb_clk_div4_en = 0; in intel_c20pll_calc_port_clock()
2391 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2394 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2400 frac = 0; in intel_c20pll_calc_port_clock()
2413 u32 val = 0; in intel_program_port_clock_ctl()
2416 lane_reversal ? XELPDP_PORT_REVERSAL : 0); in intel_program_port_clock_ctl()
2430 /* DP2.0 10G and 20G rates enable MPLLA*/ in intel_program_port_clock_ctl()
2432 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()
2434 val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()
2444 u32 val = 0; in intel_cx0_get_powerdown_update()
2445 int lane = 0; in intel_cx0_get_powerdown_update()
2455 u32 val = 0; in intel_cx0_get_powerdown_state()
2456 int lane = 0; in intel_cx0_get_powerdown_state()
2492 intel_cx0_get_powerdown_update(lane_mask), 0, in intel_cx0_powerdown_change_sequence()
2493 XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL)) in intel_cx0_powerdown_change_sequence()
2507 XELPDP_PLL_LANE_STAGGERING_DELAY(0)); in intel_cx0_setup_powerdown()
2512 u32 val = 0; in intel_cx0_get_pclk_refclk_request()
2513 int lane = 0; in intel_cx0_get_pclk_refclk_request()
2523 u32 val = 0; in intel_cx0_get_pclk_refclk_ack()
2524 int lane = 0; in intel_cx0_get_pclk_refclk_ack()
2542 XELPDP_LANE_PIPE_RESET(0) | in intel_cx0_phy_lane_reset()
2544 XELPDP_LANE_PIPE_RESET(0); in intel_cx0_phy_lane_reset()
2546 XELPDP_LANE_PHY_CURRENT_STATUS(0) | in intel_cx0_phy_lane_reset()
2548 XELPDP_LANE_PHY_CURRENT_STATUS(0); in intel_cx0_phy_lane_reset()
2553 XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2562 XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2577 XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL)) in intel_cx0_phy_lane_reset()
2585 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0); in intel_cx0_phy_lane_reset()
2603 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2670 PHY_C10_VDR_CONTROL(1), 0, in intel_cx0_program_phy_lane()
2677 u32 val = 0; in intel_cx0_get_pclk_pll_request()
2678 int lane = 0; in intel_cx0_get_pclk_pll_request()
2688 u32 val = 0; in intel_cx0_get_pclk_pll_ack()
2689 int lane = 0; in intel_cx0_get_pclk_pll_ack()
2760 XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL)) in intel_cx0pll_enable()
2822 u32 val = 0; in intel_mtl_tbt_pll_enable()
2851 100, 0, NULL)) in intel_mtl_tbt_pll_enable()
2898 * to "0" to disable PLL. in intel_cx0pll_disable()
2902 intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0); in intel_cx0pll_disable()
2904 /* 4. Program DDI_CLK_VALFREQ to 0. */ in intel_cx0pll_disable()
2905 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_cx0pll_disable()
2908 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". in intel_cx0pll_disable()
2912 intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0, in intel_cx0pll_disable()
2913 XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL)) in intel_cx0pll_disable()
2924 XELPDP_DDI_CLOCK_SELECT_MASK, 0); in intel_cx0pll_disable()
2926 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_cx0pll_disable()
2942 * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL. in intel_mtl_tbt_pll_disable()
2945 XELPDP_TBT_CLOCK_REQUEST, 0); in intel_mtl_tbt_pll_disable()
2947 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ in intel_mtl_tbt_pll_disable()
2949 XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL)) in intel_mtl_tbt_pll_disable()
2963 XELPDP_FORWARD_CLOCK_UNGATE, 0); in intel_mtl_tbt_pll_disable()
2965 /* 6. Program DDI_CLK_VALFREQ to 0. */ in intel_mtl_tbt_pll_disable()
2966 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_mtl_tbt_pll_disable()
3002 struct intel_c10pll_state mpllb_hw_state = { 0 }; in intel_c10pll_state_verify()
3028 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { in intel_c10pll_state_verify()
3032 "[CRTC:%d:%s] mismatch in C10MPLLB: Register[%d] (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3038 "[CRTC:%d:%s] mismatch in C10MPLLB: Register TX0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()
3043 "[CRTC:%d:%s] mismatch in C10MPLLB: Register CMN0 (expected 0x%02x, found 0x%02x)", in intel_c10pll_state_verify()