Lines Matching full:phy
55 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
78 enum phy phy) in icl_set_procmon_ref_values() argument
82 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
88 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
92 enum phy phy, i915_reg_t reg, u32 mask, in check_phy_reg() argument
99 "Combo PHY %c reg %08x state mismatch: " in check_phy_reg()
101 phy_name(phy), in check_phy_reg()
110 enum phy phy) in icl_verify_procmon_ref_values() argument
115 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_verify_procmon_ref_values()
118 "Combo PHY %c Voltage/Process Info : %s\n", in icl_verify_procmon_ref_values()
119 phy_name(phy), procmon->name); in icl_verify_procmon_ref_values()
121 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), in icl_verify_procmon_ref_values()
123 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), in icl_verify_procmon_ref_values()
125 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), in icl_verify_procmon_ref_values()
131 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) in has_phy_misc() argument
134 * Some platforms only expect PHY_MISC to be programmed for PHY-A and in has_phy_misc()
135 * PHY-B and may not even have instances of the register for the in has_phy_misc()
136 * other combo PHY's. in has_phy_misc()
139 * that we program it for PHY A. in has_phy_misc()
143 return phy == PHY_A; in has_phy_misc()
147 return phy < PHY_C; in has_phy_misc()
153 enum phy phy) in icl_combo_phy_enabled() argument
155 /* The PHY C added by EHL has no PHY_MISC register */ in icl_combo_phy_enabled()
156 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
157 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
159 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
161 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
172 * the PHY. So if combo PHY A is wired up to drive an external in ehl_vbt_ddi_d_present()
186 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); in ehl_vbt_ddi_d_present()
191 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) in phy_is_master() argument
206 * We must set the IREFGEN bit for any PHY acting as a master in phy_is_master()
207 * to another PHY. in phy_is_master()
209 if (phy == PHY_A) in phy_is_master()
212 return phy == PHY_D; in phy_is_master()
214 return phy == PHY_C; in phy_is_master()
220 enum phy phy) in icl_combo_phy_verify_state() argument
225 if (!icl_combo_phy_enabled(dev_priv, phy)) in icl_combo_phy_verify_state()
229 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy), in icl_combo_phy_verify_state()
235 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), in icl_combo_phy_verify_state()
239 ret &= icl_verify_procmon_ref_values(dev_priv, phy); in icl_combo_phy_verify_state()
241 if (phy_is_master(dev_priv, phy)) { in icl_combo_phy_verify_state()
242 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), in icl_combo_phy_verify_state()
249 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), in icl_combo_phy_verify_state()
255 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), in icl_combo_phy_verify_state()
262 enum phy phy, bool is_dsi, in intel_combo_phy_power_up_lanes() argument
306 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), in intel_combo_phy_power_up_lanes()
312 enum phy phy; in icl_combo_phys_init() local
314 for_each_combo_phy(dev_priv, phy) { in icl_combo_phys_init()
317 if (icl_combo_phy_verify_state(dev_priv, phy)) { in icl_combo_phys_init()
319 "Combo PHY %c already enabled, won't reprogram it.\n", in icl_combo_phys_init()
320 phy_name(phy)); in icl_combo_phys_init()
324 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_init()
328 * EHL's combo PHY A can be hooked up to either an external in icl_combo_phys_init()
331 * can't be changed on the fly, so initialize the PHY's mux in icl_combo_phys_init()
335 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
337 phy == PHY_A) { in icl_combo_phys_init()
345 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
349 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
353 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
355 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
358 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
361 icl_set_procmon_ref_values(dev_priv, phy); in icl_combo_phys_init()
363 if (phy_is_master(dev_priv, phy)) in icl_combo_phys_init()
364 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy), in icl_combo_phys_init()
367 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); in icl_combo_phys_init()
368 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), in icl_combo_phys_init()
375 enum phy phy; in icl_combo_phys_uninit() local
377 for_each_combo_phy_reverse(dev_priv, phy) { in icl_combo_phys_uninit()
378 if (phy == PHY_A && in icl_combo_phys_uninit()
379 !icl_combo_phy_verify_state(dev_priv, phy)) { in icl_combo_phys_uninit()
387 "Combo PHY %c HW state changed unexpectedly\n", in icl_combo_phys_uninit()
388 phy_name(phy)); in icl_combo_phys_uninit()
391 "Combo PHY %c HW state changed unexpectedly\n", in icl_combo_phys_uninit()
392 phy_name(phy)); in icl_combo_phys_uninit()
396 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_uninit()
399 intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0, in icl_combo_phys_uninit()
403 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); in icl_combo_phys_uninit()