Lines Matching refs:new_cdclk_state
2364 const struct intel_cdclk_state *new_cdclk_state = in intel_cdclk_pcode_pre_notify() local
2370 &new_cdclk_state->actual) && in intel_cdclk_pcode_pre_notify()
2371 new_cdclk_state->active_pipes == in intel_cdclk_pcode_pre_notify()
2378 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_pre_notify()
2379 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > in intel_cdclk_pcode_pre_notify()
2389 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); in intel_cdclk_pcode_pre_notify()
2398 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_pre_notify()
2407 const struct intel_cdclk_state *new_cdclk_state = in intel_cdclk_pcode_post_notify() local
2415 voltage_level = new_cdclk_state->actual.voltage_level; in intel_cdclk_pcode_post_notify()
2417 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2418 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < in intel_cdclk_pcode_post_notify()
2426 cdclk = new_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2435 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_post_notify()
2454 const struct intel_cdclk_state *new_cdclk_state = in intel_set_cdclk_pre_plane_update() local
2460 &new_cdclk_state->actual)) in intel_set_cdclk_pre_plane_update()
2466 if (new_cdclk_state->disable_pipes) { in intel_set_cdclk_pre_plane_update()
2467 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2470 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2471 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2472 pipe = new_cdclk_state->pipe; in intel_set_cdclk_pre_plane_update()
2478 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, in intel_set_cdclk_pre_plane_update()
2482 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2500 const struct intel_cdclk_state *new_cdclk_state = in intel_set_cdclk_post_plane_update() local
2505 &new_cdclk_state->actual)) in intel_set_cdclk_post_plane_update()
2511 if (!new_cdclk_state->disable_pipes && in intel_set_cdclk_post_plane_update()
2512 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) in intel_set_cdclk_post_plane_update()
2513 pipe = new_cdclk_state->pipe; in intel_set_cdclk_post_plane_update()
2517 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2519 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe); in intel_set_cdclk_post_plane_update()
2999 const struct intel_cdclk_state *new_cdclk_state; in intel_cdclk_atomic_check() local
3021 new_cdclk_state = intel_atomic_get_new_cdclk_state(state); in intel_cdclk_atomic_check()
3023 if (new_cdclk_state && in intel_cdclk_atomic_check()
3024 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) in intel_cdclk_atomic_check()
3046 const struct intel_cdclk_state *new_cdclk_state) in intel_cdclk_need_serialize() argument
3049 hweight8(new_cdclk_state->active_pipes); in intel_cdclk_need_serialize()
3051 &new_cdclk_state->actual); in intel_cdclk_need_serialize()
3063 struct intel_cdclk_state *new_cdclk_state; in intel_modeset_calc_cdclk() local
3067 new_cdclk_state = intel_atomic_get_cdclk_state(state); in intel_modeset_calc_cdclk()
3068 if (IS_ERR(new_cdclk_state)) in intel_modeset_calc_cdclk()
3069 return PTR_ERR(new_cdclk_state); in intel_modeset_calc_cdclk()
3073 new_cdclk_state->active_pipes = in intel_modeset_calc_cdclk()
3076 ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); in intel_modeset_calc_cdclk()
3080 if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) { in intel_modeset_calc_cdclk()
3085 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3088 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || in intel_modeset_calc_cdclk()
3089 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || in intel_modeset_calc_cdclk()
3091 &new_cdclk_state->logical)) { in intel_modeset_calc_cdclk()
3092 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3099 if (is_power_of_2(new_cdclk_state->active_pipes) && in intel_modeset_calc_cdclk()
3102 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3106 pipe = ilog2(new_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
3119 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3124 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3129 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3133 new_cdclk_state->pipe = pipe; in intel_modeset_calc_cdclk()
3139 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3145 new_cdclk_state->disable_pipes = true; in intel_modeset_calc_cdclk()
3153 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
3154 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
3157 new_cdclk_state->logical.voltage_level, in intel_modeset_calc_cdclk()
3158 new_cdclk_state->actual.voltage_level); in intel_modeset_calc_cdclk()