Lines Matching refs:cdclk_config
73 struct intel_cdclk_config *cdclk_config);
75 const struct intel_cdclk_config *cdclk_config,
82 struct intel_cdclk_config *cdclk_config) in intel_cdclk_get_cdclk() argument
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
88 const struct intel_cdclk_config *cdclk_config, in intel_cdclk_set_cdclk() argument
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
95 struct intel_cdclk_state *cdclk_config) in intel_cdclk_modeset_calc_cdclk() argument
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
107 struct intel_cdclk_config *cdclk_config) in fixed_133mhz_get_cdclk() argument
109 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
113 struct intel_cdclk_config *cdclk_config) in fixed_200mhz_get_cdclk() argument
115 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
119 struct intel_cdclk_config *cdclk_config) in fixed_266mhz_get_cdclk() argument
121 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
125 struct intel_cdclk_config *cdclk_config) in fixed_333mhz_get_cdclk() argument
127 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
131 struct intel_cdclk_config *cdclk_config) in fixed_400mhz_get_cdclk() argument
133 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
137 struct intel_cdclk_config *cdclk_config) in fixed_450mhz_get_cdclk() argument
139 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
143 struct intel_cdclk_config *cdclk_config) in i85x_get_cdclk() argument
154 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
168 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
171 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
174 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
179 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
185 struct intel_cdclk_config *cdclk_config) in i915gm_get_cdclk() argument
193 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
199 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
203 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
209 struct intel_cdclk_config *cdclk_config) in i945gm_get_cdclk() argument
217 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
223 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
227 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
303 struct intel_cdclk_config *cdclk_config) in g33_get_cdclk() argument
314 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
323 switch (cdclk_config->vco) { in g33_get_cdclk()
340 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
347 cdclk_config->vco, tmp); in g33_get_cdclk()
348 cdclk_config->cdclk = 190476; in g33_get_cdclk()
352 struct intel_cdclk_config *cdclk_config) in pnv_get_cdclk() argument
361 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
364 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
367 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
370 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
377 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
380 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
386 struct intel_cdclk_config *cdclk_config) in i965gm_get_cdclk() argument
396 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
405 switch (cdclk_config->vco) { in i965gm_get_cdclk()
419 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
426 cdclk_config->vco, tmp); in i965gm_get_cdclk()
427 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
431 struct intel_cdclk_config *cdclk_config) in gm45_get_cdclk() argument
437 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
443 switch (cdclk_config->vco) { in gm45_get_cdclk()
447 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
450 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
455 cdclk_config->vco, tmp); in gm45_get_cdclk()
456 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
462 struct intel_cdclk_config *cdclk_config) in hsw_get_cdclk() argument
468 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
470 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
472 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
474 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
476 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
519 struct intel_cdclk_config *cdclk_config) in vlv_get_cdclk() argument
526 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
527 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
529 cdclk_config->vco); in vlv_get_cdclk()
537 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
540 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
582 const struct intel_cdclk_config *cdclk_config, in vlv_set_cdclk() argument
585 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
586 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
671 const struct intel_cdclk_config *cdclk_config, in chv_set_cdclk() argument
674 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
675 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
746 struct intel_cdclk_config *cdclk_config) in bdw_get_cdclk() argument
752 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
754 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
756 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
758 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
760 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
762 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
768 cdclk_config->voltage_level = in bdw_get_cdclk()
769 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
790 const struct intel_cdclk_config *cdclk_config, in bdw_set_cdclk() argument
793 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
834 cdclk_config->voltage_level); in bdw_set_cdclk()
878 struct intel_cdclk_config *cdclk_config) in skl_dpll0_update() argument
882 cdclk_config->ref = 24000; in skl_dpll0_update()
883 cdclk_config->vco = 0; in skl_dpll0_update()
906 cdclk_config->vco = 8100000; in skl_dpll0_update()
910 cdclk_config->vco = 8640000; in skl_dpll0_update()
919 struct intel_cdclk_config *cdclk_config) in skl_get_cdclk() argument
923 skl_dpll0_update(dev_priv, cdclk_config); in skl_get_cdclk()
925 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
927 if (cdclk_config->vco == 0) in skl_get_cdclk()
932 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
935 cdclk_config->cdclk = 432000; in skl_get_cdclk()
938 cdclk_config->cdclk = 308571; in skl_get_cdclk()
941 cdclk_config->cdclk = 540000; in skl_get_cdclk()
944 cdclk_config->cdclk = 617143; in skl_get_cdclk()
953 cdclk_config->cdclk = 450000; in skl_get_cdclk()
956 cdclk_config->cdclk = 337500; in skl_get_cdclk()
959 cdclk_config->cdclk = 540000; in skl_get_cdclk()
962 cdclk_config->cdclk = 675000; in skl_get_cdclk()
975 cdclk_config->voltage_level = in skl_get_cdclk()
976 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
1072 const struct intel_cdclk_config *cdclk_config, in skl_set_cdclk() argument
1075 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1076 int vco = cdclk_config->vco; in skl_set_cdclk()
1138 cdclk_config->voltage_level); in skl_set_cdclk()
1187 struct intel_cdclk_config cdclk_config; in skl_cdclk_init_hw() local
1203 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1205 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1206 if (cdclk_config.vco == 0) in skl_cdclk_init_hw()
1207 cdclk_config.vco = 8100000; in skl_cdclk_init_hw()
1208 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco); in skl_cdclk_init_hw()
1209 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_init_hw()
1211 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_init_hw()
1216 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw() local
1218 cdclk_config.cdclk = cdclk_config.bypass; in skl_cdclk_uninit_hw()
1219 cdclk_config.vco = 0; in skl_cdclk_uninit_hw()
1220 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk); in skl_cdclk_uninit_hw()
1222 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in skl_cdclk_uninit_hw()
1470 struct intel_cdclk_config *cdclk_config) in icl_readout_refclk() argument
1479 cdclk_config->ref = 24000; in icl_readout_refclk()
1482 cdclk_config->ref = 19200; in icl_readout_refclk()
1485 cdclk_config->ref = 38400; in icl_readout_refclk()
1491 struct intel_cdclk_config *cdclk_config) in bxt_de_pll_readout() argument
1496 cdclk_config->ref = 38400; in bxt_de_pll_readout()
1498 icl_readout_refclk(dev_priv, cdclk_config); in bxt_de_pll_readout()
1500 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1509 cdclk_config->vco = 0; in bxt_de_pll_readout()
1522 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1526 struct intel_cdclk_config *cdclk_config) in bxt_get_cdclk() argument
1532 bxt_de_pll_readout(dev_priv, cdclk_config); in bxt_get_cdclk()
1535 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1537 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1539 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1541 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1542 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1576 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1577 cdclk_config->vco, size * div); in bxt_get_cdclk()
1579 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1587 cdclk_config->voltage_level = in bxt_get_cdclk()
1588 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1849 const struct intel_cdclk_config *cdclk_config, in _bxt_set_cdclk() argument
1852 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk()
1853 int vco = cdclk_config->vco; in _bxt_set_cdclk()
1899 const struct intel_cdclk_config *cdclk_config, in bxt_set_cdclk() argument
1903 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
1936 cdclk_config, &mid_cdclk_config)) { in bxt_set_cdclk()
1938 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
1940 _bxt_set_cdclk(dev_priv, cdclk_config, pipe); in bxt_set_cdclk()
1950 cdclk_config->voltage_level); in bxt_set_cdclk()
1960 cdclk_config->voltage_level, in bxt_set_cdclk()
1977 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
2051 struct intel_cdclk_config cdclk_config; in bxt_cdclk_init_hw() local
2059 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2066 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0); in bxt_cdclk_init_hw()
2067 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2068 cdclk_config.voltage_level = in bxt_cdclk_init_hw()
2069 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_init_hw()
2071 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_init_hw()
2076 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw() local
2078 cdclk_config.cdclk = cdclk_config.bypass; in bxt_cdclk_uninit_hw()
2079 cdclk_config.vco = 0; in bxt_cdclk_uninit_hw()
2080 cdclk_config.voltage_level = in bxt_cdclk_uninit_hw()
2081 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk); in bxt_cdclk_uninit_hw()
2083 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE); in bxt_cdclk_uninit_hw()
2249 const struct intel_cdclk_config *cdclk_config, in intel_cdclk_dump_config() argument
2253 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2254 cdclk_config->ref, cdclk_config->bypass, in intel_cdclk_dump_config()
2255 cdclk_config->voltage_level); in intel_cdclk_dump_config()
2300 const struct intel_cdclk_config *cdclk_config, in intel_set_cdclk() argument
2305 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2311 intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to"); in intel_set_cdclk()
2334 intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe); in intel_set_cdclk()
2352 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2355 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]"); in intel_set_cdclk()
2456 struct intel_cdclk_config cdclk_config; in intel_set_cdclk_pre_plane_update() local
2467 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2471 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2474 cdclk_config = old_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2478 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, in intel_set_cdclk_pre_plane_update()
2484 intel_set_cdclk(i915, &cdclk_config, pipe); in intel_set_cdclk_pre_plane_update()