Lines Matching +full:refclk +full:- +full:frequency
2 * Copyright © 2006-2017 Intel Corporation
51 * CDCLK clocks most of the display pipe logic, and thus its frequency
56 * On several platforms the CDCLK frequency can be changed dynamically
58 * Typically changes to the CDCLK frequency require all the display pipes
59 * to be shut down while the frequency is being changed.
62 * DMC will not change the active CDCLK frequency however, so that part
65 * RAWCLK is a fixed frequency clock, often used by various auxiliary
67 * really need to know about RAWCLK is its frequency so that various
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
103 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
109 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
115 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
121 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
127 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
133 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
139 cdclk_config->cdclk = 450000; in fixed_450mhz_get_cdclk()
145 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i85x_get_cdclk()
153 if (pdev->revision == 0x1) { in i85x_get_cdclk()
154 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
158 pci_bus_read_config_word(pdev->bus, in i85x_get_cdclk()
168 cdclk_config->cdclk = 200000; in i85x_get_cdclk()
171 cdclk_config->cdclk = 250000; in i85x_get_cdclk()
174 cdclk_config->cdclk = 133333; in i85x_get_cdclk()
179 cdclk_config->cdclk = 266667; in i85x_get_cdclk()
187 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i915gm_get_cdclk()
193 cdclk_config->cdclk = 133333; in i915gm_get_cdclk()
199 cdclk_config->cdclk = 333333; in i915gm_get_cdclk()
203 cdclk_config->cdclk = 190000; in i915gm_get_cdclk()
211 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i945gm_get_cdclk()
217 cdclk_config->cdclk = 133333; in i945gm_get_cdclk()
223 cdclk_config->cdclk = 320000; in i945gm_get_cdclk()
227 cdclk_config->cdclk = 200000; in i945gm_get_cdclk()
294 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n", in intel_hpll_vco()
297 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco); in intel_hpll_vco()
305 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in g33_get_cdclk()
314 cdclk_config->vco = intel_hpll_vco(dev_priv); in g33_get_cdclk()
323 switch (cdclk_config->vco) { in g33_get_cdclk()
340 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in g33_get_cdclk()
345 drm_err(&dev_priv->drm, in g33_get_cdclk()
347 cdclk_config->vco, tmp); in g33_get_cdclk()
348 cdclk_config->cdclk = 190476; in g33_get_cdclk()
354 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in pnv_get_cdclk()
361 cdclk_config->cdclk = 266667; in pnv_get_cdclk()
364 cdclk_config->cdclk = 333333; in pnv_get_cdclk()
367 cdclk_config->cdclk = 444444; in pnv_get_cdclk()
370 cdclk_config->cdclk = 200000; in pnv_get_cdclk()
373 drm_err(&dev_priv->drm, in pnv_get_cdclk()
377 cdclk_config->cdclk = 133333; in pnv_get_cdclk()
380 cdclk_config->cdclk = 166667; in pnv_get_cdclk()
388 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in i965gm_get_cdclk()
396 cdclk_config->vco = intel_hpll_vco(dev_priv); in i965gm_get_cdclk()
400 cdclk_sel = ((tmp >> 8) & 0x1f) - 1; in i965gm_get_cdclk()
405 switch (cdclk_config->vco) { in i965gm_get_cdclk()
419 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, in i965gm_get_cdclk()
424 drm_err(&dev_priv->drm, in i965gm_get_cdclk()
426 cdclk_config->vco, tmp); in i965gm_get_cdclk()
427 cdclk_config->cdclk = 200000; in i965gm_get_cdclk()
433 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); in gm45_get_cdclk()
437 cdclk_config->vco = intel_hpll_vco(dev_priv); in gm45_get_cdclk()
443 switch (cdclk_config->vco) { in gm45_get_cdclk()
447 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222; in gm45_get_cdclk()
450 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571; in gm45_get_cdclk()
453 drm_err(&dev_priv->drm, in gm45_get_cdclk()
455 cdclk_config->vco, tmp); in gm45_get_cdclk()
456 cdclk_config->cdclk = 222222; in gm45_get_cdclk()
468 cdclk_config->cdclk = 800000; in hsw_get_cdclk()
470 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
472 cdclk_config->cdclk = 450000; in hsw_get_cdclk()
474 cdclk_config->cdclk = 337500; in hsw_get_cdclk()
476 cdclk_config->cdclk = 540000; in hsw_get_cdclk()
481 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? in vlv_calc_cdclk()
514 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in vlv_calc_voltage_level()
526 cdclk_config->vco = vlv_get_hpll_vco(dev_priv); in vlv_get_cdclk()
527 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk", in vlv_get_cdclk()
529 cdclk_config->vco); in vlv_get_cdclk()
537 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >> in vlv_get_cdclk()
540 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >> in vlv_get_cdclk()
553 if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
564 * WA - write default credits before re-programming in vlv_program_pfi_credits()
577 drm_WARN_ON(&dev_priv->drm, in vlv_program_pfi_credits()
585 int cdclk = cdclk_config->cdclk; in vlv_set_cdclk()
586 u32 val, cmd = cdclk_config->voltage_level; in vlv_set_cdclk()
602 * off and a CDCLK frequency other than the minimum, like when in vlv_set_cdclk()
621 drm_err(&dev_priv->drm, in vlv_set_cdclk()
628 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, in vlv_set_cdclk()
629 cdclk) - 1; in vlv_set_cdclk()
640 drm_err(&dev_priv->drm, in vlv_set_cdclk()
644 /* adjust self-refresh exit latency value */ in vlv_set_cdclk()
674 int cdclk = cdclk_config->cdclk; in chv_set_cdclk()
675 u32 val, cmd = cdclk_config->voltage_level; in chv_set_cdclk()
690 * off and a CDCLK frequency other than the minimum, like when in chv_set_cdclk()
705 drm_err(&dev_priv->drm, in chv_set_cdclk()
752 cdclk_config->cdclk = 800000; in bdw_get_cdclk()
754 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
756 cdclk_config->cdclk = 450000; in bdw_get_cdclk()
758 cdclk_config->cdclk = 540000; in bdw_get_cdclk()
760 cdclk_config->cdclk = 337500; in bdw_get_cdclk()
762 cdclk_config->cdclk = 675000; in bdw_get_cdclk()
766 * at least what the CDCLK frequency requires. in bdw_get_cdclk()
768 cdclk_config->voltage_level = in bdw_get_cdclk()
769 bdw_calc_voltage_level(cdclk_config->cdclk); in bdw_get_cdclk()
793 int cdclk = cdclk_config->cdclk; in bdw_set_cdclk()
796 if (drm_WARN(&dev_priv->drm, in bdw_set_cdclk()
802 "trying to change cdclk frequency with cdclk not enabled\n")) in bdw_set_cdclk()
805 ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
807 drm_err(&dev_priv->drm, in bdw_set_cdclk()
821 drm_err(&dev_priv->drm, "Switching to FCLK failed\n"); in bdw_set_cdclk()
831 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n"); in bdw_set_cdclk()
833 snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
834 cdclk_config->voltage_level); in bdw_set_cdclk()
837 DIV_ROUND_CLOSEST(cdclk, 1000) - 1); in bdw_set_cdclk()
882 cdclk_config->ref = 24000; in skl_dpll0_update()
883 cdclk_config->vco = 0; in skl_dpll0_update()
889 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0)) in skl_dpll0_update()
894 if (drm_WARN_ON(&dev_priv->drm, in skl_dpll0_update()
906 cdclk_config->vco = 8100000; in skl_dpll0_update()
910 cdclk_config->vco = 8640000; in skl_dpll0_update()
925 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref; in skl_get_cdclk()
927 if (cdclk_config->vco == 0) in skl_get_cdclk()
932 if (cdclk_config->vco == 8640000) { in skl_get_cdclk()
935 cdclk_config->cdclk = 432000; in skl_get_cdclk()
938 cdclk_config->cdclk = 308571; in skl_get_cdclk()
941 cdclk_config->cdclk = 540000; in skl_get_cdclk()
944 cdclk_config->cdclk = 617143; in skl_get_cdclk()
953 cdclk_config->cdclk = 450000; in skl_get_cdclk()
956 cdclk_config->cdclk = 337500; in skl_get_cdclk()
959 cdclk_config->cdclk = 540000; in skl_get_cdclk()
962 cdclk_config->cdclk = 675000; in skl_get_cdclk()
973 * at least what the CDCLK frequency requires. in skl_get_cdclk()
975 cdclk_config->voltage_level = in skl_get_cdclk()
976 skl_calc_voltage_level(cdclk_config->cdclk); in skl_get_cdclk()
979 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
982 return DIV_ROUND_CLOSEST(cdclk - 1000, 500); in skl_cdclk_decimal()
988 bool changed = dev_priv->skl_preferred_vco_freq != vco; in skl_set_preferred_cdclk_vco()
990 dev_priv->skl_preferred_vco_freq = vco; in skl_set_preferred_cdclk_vco()
998 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in skl_dpll0_link_rate()
1003 * desired frequency. The usual DP link rates operate with a VCO of in skl_dpll0_link_rate()
1006 * rate later on, with the constraint of choosing a frequency that in skl_dpll0_link_rate()
1029 drm_err(&dev_priv->drm, "DPLL0 not locked\n"); in skl_dpll0_enable()
1031 dev_priv->display.cdclk.hw.vco = vco; in skl_dpll0_enable()
1043 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n"); in skl_dpll0_disable()
1045 dev_priv->display.cdclk.hw.vco = 0; in skl_dpll0_disable()
1053 drm_WARN_ON(&dev_priv->drm, in skl_cdclk_freq_sel()
1054 cdclk != dev_priv->display.cdclk.hw.bypass); in skl_cdclk_freq_sel()
1055 drm_WARN_ON(&dev_priv->drm, vco != 0); in skl_cdclk_freq_sel()
1075 int cdclk = cdclk_config->cdclk; in skl_set_cdclk()
1076 int vco = cdclk_config->vco; in skl_set_cdclk()
1088 drm_WARN_ON_ONCE(&dev_priv->drm, in skl_set_cdclk()
1091 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1096 drm_err(&dev_priv->drm, in skl_set_cdclk()
1103 if (dev_priv->display.cdclk.hw.vco != 0 && in skl_set_cdclk()
1104 dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1109 if (dev_priv->display.cdclk.hw.vco != vco) { in skl_set_cdclk()
1121 if (dev_priv->display.cdclk.hw.vco != vco) in skl_set_cdclk()
1137 snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
1138 cdclk_config->voltage_level); in skl_set_cdclk()
1148 * check if the pre-os initialized the display in skl_sanitize_cdclk()
1150 * pre-os which can be used by the OS drivers to check the status in skl_sanitize_cdclk()
1156 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in skl_sanitize_cdclk()
1159 if (dev_priv->display.cdclk.hw.vco == 0 || in skl_sanitize_cdclk()
1160 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in skl_sanitize_cdclk()
1166 * decimal part is programmed wrong from BIOS where pre-os does not in skl_sanitize_cdclk()
1171 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk); in skl_sanitize_cdclk()
1177 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in skl_sanitize_cdclk()
1180 dev_priv->display.cdclk.hw.cdclk = 0; in skl_sanitize_cdclk()
1182 dev_priv->display.cdclk.hw.vco = -1; in skl_sanitize_cdclk()
1191 if (dev_priv->display.cdclk.hw.cdclk != 0 && in skl_cdclk_init_hw()
1192 dev_priv->display.cdclk.hw.vco != 0) { in skl_cdclk_init_hw()
1197 if (dev_priv->skl_preferred_vco_freq == 0) in skl_cdclk_init_hw()
1199 dev_priv->display.cdclk.hw.vco); in skl_cdclk_init_hw()
1203 cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_init_hw()
1205 cdclk_config.vco = dev_priv->skl_preferred_vco_freq; in skl_cdclk_init_hw()
1216 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in skl_cdclk_uninit_hw()
1227 u16 refclk; member
1234 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1235 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1236 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1237 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1238 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1243 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1244 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1245 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1250 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1251 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1252 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1253 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1254 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1255 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1257 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1258 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1259 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1260 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1261 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1262 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1264 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1265 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1266 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1267 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1268 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1269 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1274 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
1275 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
1276 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
1277 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
1278 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
1279 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
1281 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
1282 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
1283 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
1284 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
1285 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
1286 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
1288 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
1289 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
1290 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
1291 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
1292 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
1293 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
1298 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1299 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1300 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1302 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1303 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1304 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1306 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1307 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1308 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1313 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1314 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1315 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1316 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1317 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1319 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1320 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1321 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1322 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1323 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1325 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1326 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1327 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1328 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1329 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1334 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1335 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1336 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1337 { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
1338 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1339 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1341 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1342 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1343 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1344 { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
1345 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1346 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1348 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1349 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1350 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1351 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
1352 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1353 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1358 { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
1359 { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
1360 { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
1361 { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
1362 { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
1363 { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
1364 { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
1365 { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
1366 { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
1367 { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
1368 { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1369 { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1370 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1375 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
1376 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
1377 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
1378 { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
1379 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
1380 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
1386 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk()
1389 for (i = 0; table[i].refclk; i++) in bxt_calc_cdclk()
1390 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk()
1394 drm_WARN(&dev_priv->drm, 1, in bxt_calc_cdclk()
1395 "Cannot satisfy minimum cdclk %d with refclk %u\n", in bxt_calc_cdclk()
1396 min_cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk()
1402 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in bxt_calc_cdclk_pll_vco()
1405 if (cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_calc_cdclk_pll_vco()
1408 for (i = 0; table[i].refclk; i++) in bxt_calc_cdclk_pll_vco()
1409 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in bxt_calc_cdclk_pll_vco()
1411 return dev_priv->display.cdclk.hw.ref * table[i].ratio; in bxt_calc_cdclk_pll_vco()
1413 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in bxt_calc_cdclk_pll_vco()
1414 cdclk, dev_priv->display.cdclk.hw.ref); in bxt_calc_cdclk_pll_vco()
1479 cdclk_config->ref = 24000; in icl_readout_refclk()
1482 cdclk_config->ref = 19200; in icl_readout_refclk()
1485 cdclk_config->ref = 38400; in icl_readout_refclk()
1496 cdclk_config->ref = 38400; in bxt_de_pll_readout()
1500 cdclk_config->ref = 19200; in bxt_de_pll_readout()
1509 cdclk_config->vco = 0; in bxt_de_pll_readout()
1522 cdclk_config->vco = ratio * cdclk_config->ref; in bxt_de_pll_readout()
1535 cdclk_config->bypass = cdclk_config->ref / 2; in bxt_get_cdclk()
1537 cdclk_config->bypass = 50000; in bxt_get_cdclk()
1539 cdclk_config->bypass = cdclk_config->ref; in bxt_get_cdclk()
1541 if (cdclk_config->vco == 0) { in bxt_get_cdclk()
1542 cdclk_config->cdclk = cdclk_config->bypass; in bxt_get_cdclk()
1574 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size); in bxt_get_cdclk()
1576 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) * in bxt_get_cdclk()
1577 cdclk_config->vco, size * div); in bxt_get_cdclk()
1579 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div); in bxt_get_cdclk()
1585 * at least what the CDCLK frequency requires. in bxt_get_cdclk()
1587 cdclk_config->voltage_level = in bxt_get_cdclk()
1588 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk); in bxt_get_cdclk()
1598 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n"); in bxt_de_pll_disable()
1600 dev_priv->display.cdclk.hw.vco = 0; in bxt_de_pll_disable()
1605 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in bxt_de_pll_enable()
1615 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n"); in bxt_de_pll_enable()
1617 dev_priv->display.cdclk.hw.vco = vco; in bxt_de_pll_enable()
1627 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n"); in icl_cdclk_pll_disable()
1629 dev_priv->display.cdclk.hw.vco = 0; in icl_cdclk_pll_disable()
1634 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in icl_cdclk_pll_enable()
1645 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n"); in icl_cdclk_pll_enable()
1647 dev_priv->display.cdclk.hw.vco = vco; in icl_cdclk_pll_enable()
1652 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref); in adlp_cdclk_pll_crawl()
1666 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n"); in adlp_cdclk_pll_crawl()
1671 dev_priv->display.cdclk.hw.vco = vco; in adlp_cdclk_pll_crawl()
1700 drm_WARN_ON(&dev_priv->drm, in bxt_cdclk_cd2x_div_sel()
1701 cdclk != dev_priv->display.cdclk.hw.bypass); in bxt_cdclk_cd2x_div_sel()
1702 drm_WARN_ON(&dev_priv->drm, vco != 0); in bxt_cdclk_cd2x_div_sel()
1718 const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table; in cdclk_squash_waveform()
1721 if (cdclk == dev_priv->display.cdclk.hw.bypass) in cdclk_squash_waveform()
1724 for (i = 0; table[i].refclk; i++) in cdclk_squash_waveform()
1725 if (table[i].refclk == dev_priv->display.cdclk.hw.ref && in cdclk_squash_waveform()
1729 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n", in cdclk_squash_waveform()
1730 cdclk, dev_priv->display.cdclk.hw.ref); in cdclk_squash_waveform()
1737 if (i915->display.cdclk.hw.vco != 0 && in icl_cdclk_pll_update()
1738 i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1741 if (i915->display.cdclk.hw.vco != vco) in icl_cdclk_pll_update()
1747 if (i915->display.cdclk.hw.vco != 0 && in bxt_cdclk_pll_update()
1748 i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1751 if (i915->display.cdclk.hw.vco != vco) in bxt_cdclk_pll_update()
1791 /* Return if PLL is in an unknown state, force a complete disable and re-enable. */ in cdclk_compute_crawl_and_squash_midpoint()
1792 if (cdclk_pll_is_unknown(old_cdclk_config->vco)) in cdclk_compute_crawl_and_squash_midpoint()
1799 old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1800 new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk); in cdclk_compute_crawl_and_squash_midpoint()
1803 if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 || in cdclk_compute_crawl_and_squash_midpoint()
1804 old_cdclk_config->vco == new_cdclk_config->vco || in cdclk_compute_crawl_and_squash_midpoint()
1812 * - If moving to a higher cdclk, the desired action is squashing. in cdclk_compute_crawl_and_squash_midpoint()
1814 * - If moving to a lower cdclk, the desired action is crawling. in cdclk_compute_crawl_and_squash_midpoint()
1819 mid_cdclk_config->vco = old_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
1822 mid_cdclk_config->vco = new_cdclk_config->vco; in cdclk_compute_crawl_and_squash_midpoint()
1826 mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) * in cdclk_compute_crawl_and_squash_midpoint()
1827 mid_cdclk_config->vco, size * div); in cdclk_compute_crawl_and_squash_midpoint()
1831 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk < in cdclk_compute_crawl_and_squash_midpoint()
1832 min(old_cdclk_config->cdclk, new_cdclk_config->cdclk)); in cdclk_compute_crawl_and_squash_midpoint()
1833 drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk > in cdclk_compute_crawl_and_squash_midpoint()
1834 i915->display.cdclk.max_cdclk_freq); in cdclk_compute_crawl_and_squash_midpoint()
1835 drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) != in cdclk_compute_crawl_and_squash_midpoint()
1844 dev_priv->display.cdclk.hw.vco > 0 && in pll_enable_wa_needed()
1852 int cdclk = cdclk_config->cdclk; in _bxt_set_cdclk()
1853 int vco = cdclk_config->vco; in _bxt_set_cdclk()
1858 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 && in _bxt_set_cdclk()
1859 !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) { in _bxt_set_cdclk()
1860 if (dev_priv->display.cdclk.hw.vco != vco) in _bxt_set_cdclk()
1886 * Disable SSA Precharge when CD clock frequency < 500 MHz, in _bxt_set_cdclk()
1903 int cdclk = cdclk_config->cdclk; in bxt_set_cdclk()
1907 * Inform power controller of upcoming frequency change. in bxt_set_cdclk()
1915 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1924 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
1929 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1935 if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw, in bxt_set_cdclk()
1945 * NOOP - No Pcode communication needed for in bxt_set_cdclk()
1949 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
1950 cdclk_config->voltage_level); in bxt_set_cdclk()
1958 ret = snb_pcode_write_timeout(&dev_priv->uncore, in bxt_set_cdclk()
1960 cdclk_config->voltage_level, in bxt_set_cdclk()
1964 drm_err(&dev_priv->drm, in bxt_set_cdclk()
1977 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level; in bxt_set_cdclk()
1986 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK"); in bxt_sanitize_cdclk()
1988 if (dev_priv->display.cdclk.hw.vco == 0 || in bxt_sanitize_cdclk()
1989 dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass) in bxt_sanitize_cdclk()
1994 * Some BIOS versions leave an incorrect decimal frequency value and in bxt_sanitize_cdclk()
2007 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk); in bxt_sanitize_cdclk()
2008 if (cdclk != dev_priv->display.cdclk.hw.cdclk) in bxt_sanitize_cdclk()
2013 if (vco != dev_priv->display.cdclk.hw.vco) in bxt_sanitize_cdclk()
2020 clock = dev_priv->display.cdclk.hw.vco / 2; in bxt_sanitize_cdclk()
2022 clock = dev_priv->display.cdclk.hw.cdclk; in bxt_sanitize_cdclk()
2025 dev_priv->display.cdclk.hw.vco); in bxt_sanitize_cdclk()
2028 * Disable SSA Precharge when CD clock frequency < 500 MHz, in bxt_sanitize_cdclk()
2032 dev_priv->display.cdclk.hw.cdclk >= 500000) in bxt_sanitize_cdclk()
2040 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n"); in bxt_sanitize_cdclk()
2043 dev_priv->display.cdclk.hw.cdclk = 0; in bxt_sanitize_cdclk()
2046 dev_priv->display.cdclk.hw.vco = -1; in bxt_sanitize_cdclk()
2055 if (dev_priv->display.cdclk.hw.cdclk != 0 && in bxt_cdclk_init_hw()
2056 dev_priv->display.cdclk.hw.vco != 0) in bxt_cdclk_init_hw()
2059 cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_init_hw()
2063 * - The initial CDCLK needs to be read from VBT. in bxt_cdclk_init_hw()
2076 struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw; in bxt_cdclk_uninit_hw()
2087 * intel_cdclk_init_hw - Initialize CDCLK hardware
2090 * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2104 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2125 drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco)); in intel_cdclk_can_crawl_and_squash()
2127 if (a->vco == 0 || b->vco == 0) in intel_cdclk_can_crawl_and_squash()
2133 old_waveform = cdclk_squash_waveform(i915, a->cdclk); in intel_cdclk_can_crawl_and_squash()
2134 new_waveform = cdclk_squash_waveform(i915, b->cdclk); in intel_cdclk_can_crawl_and_squash()
2136 return a->vco != b->vco && in intel_cdclk_can_crawl_and_squash()
2153 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk); in intel_cdclk_can_crawl()
2154 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk); in intel_cdclk_can_crawl()
2156 return a->vco != 0 && b->vco != 0 && in intel_cdclk_can_crawl()
2157 a->vco != b->vco && in intel_cdclk_can_crawl()
2159 a->ref == b->ref; in intel_cdclk_can_crawl()
2175 return a->cdclk != b->cdclk && in intel_cdclk_can_squash()
2176 a->vco != 0 && in intel_cdclk_can_squash()
2177 a->vco == b->vco && in intel_cdclk_can_squash()
2178 a->ref == b->ref; in intel_cdclk_can_squash()
2182 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
2194 return a->cdclk != b->cdclk || in intel_cdclk_needs_modeset()
2195 a->vco != b->vco || in intel_cdclk_needs_modeset()
2196 a->ref != b->ref; in intel_cdclk_needs_modeset()
2200 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2227 return a->cdclk != b->cdclk && in intel_cdclk_can_cd2x_update()
2228 a->vco != 0 && in intel_cdclk_can_cd2x_update()
2229 a->vco == b->vco && in intel_cdclk_can_cd2x_update()
2230 a->ref == b->ref; in intel_cdclk_can_cd2x_update()
2234 * intel_cdclk_changed - Determine if two CDCLK configurations are different
2245 a->voltage_level != b->voltage_level; in intel_cdclk_changed()
2252 drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n", in intel_cdclk_dump_config()
2253 context, cdclk_config->cdclk, cdclk_config->vco, in intel_cdclk_dump_config()
2254 cdclk_config->ref, cdclk_config->bypass, in intel_cdclk_dump_config()
2255 cdclk_config->voltage_level); in intel_cdclk_dump_config()
2279 ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL, in intel_pcode_notify()
2285 drm_err(&i915->drm, in intel_pcode_notify()
2291 * intel_set_cdclk - Push the CDCLK configuration to the hardware
2305 if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config)) in intel_set_cdclk()
2308 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk)) in intel_set_cdclk()
2313 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2326 mutex_lock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2327 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2330 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex, in intel_set_cdclk()
2331 &dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2336 for_each_intel_dp(&dev_priv->drm, encoder) { in intel_set_cdclk()
2339 mutex_unlock(&intel_dp->aux.hw_mutex); in intel_set_cdclk()
2341 mutex_unlock(&dev_priv->display.gmbus.mutex); in intel_set_cdclk()
2343 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { in intel_set_cdclk()
2351 if (drm_WARN(&dev_priv->drm, in intel_set_cdclk()
2352 intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config), in intel_set_cdclk()
2354 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]"); in intel_set_cdclk()
2361 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_cdclk_pcode_pre_notify()
2369 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_cdclk_pcode_pre_notify()
2370 &new_cdclk_state->actual) && in intel_cdclk_pcode_pre_notify()
2371 new_cdclk_state->active_pipes == in intel_cdclk_pcode_pre_notify()
2372 old_cdclk_state->active_pipes) in intel_cdclk_pcode_pre_notify()
2375 /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */ in intel_cdclk_pcode_pre_notify()
2378 change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_pre_notify()
2379 update_pipe_count = hweight8(new_cdclk_state->active_pipes) > in intel_cdclk_pcode_pre_notify()
2380 hweight8(old_cdclk_state->active_pipes); in intel_cdclk_pcode_pre_notify()
2383 * According to "Sequence Before Frequency Change", in intel_cdclk_pcode_pre_notify()
2389 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); in intel_cdclk_pcode_pre_notify()
2398 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_pre_notify()
2406 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_cdclk_pcode_post_notify()
2414 /* According to "Sequence After Frequency Change", set voltage to used level */ in intel_cdclk_pcode_post_notify()
2415 voltage_level = new_cdclk_state->actual.voltage_level; in intel_cdclk_pcode_post_notify()
2417 update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2418 update_pipe_count = hweight8(new_cdclk_state->active_pipes) < in intel_cdclk_pcode_post_notify()
2419 hweight8(old_cdclk_state->active_pipes); in intel_cdclk_pcode_post_notify()
2422 * According to "Sequence After Frequency Change", in intel_cdclk_pcode_post_notify()
2426 cdclk = new_cdclk_state->actual.cdclk; in intel_cdclk_pcode_post_notify()
2435 num_active_pipes = hweight8(new_cdclk_state->active_pipes); in intel_cdclk_pcode_post_notify()
2442 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2451 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_set_cdclk_pre_plane_update()
2459 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_pre_plane_update()
2460 &new_cdclk_state->actual)) in intel_set_cdclk_pre_plane_update()
2466 if (new_cdclk_state->disable_pipes) { in intel_set_cdclk_pre_plane_update()
2467 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2470 if (new_cdclk_state->actual.cdclk >= old_cdclk_state->actual.cdclk) { in intel_set_cdclk_pre_plane_update()
2471 cdclk_config = new_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2472 pipe = new_cdclk_state->pipe; in intel_set_cdclk_pre_plane_update()
2474 cdclk_config = old_cdclk_state->actual; in intel_set_cdclk_pre_plane_update()
2478 cdclk_config.voltage_level = max(new_cdclk_state->actual.voltage_level, in intel_set_cdclk_pre_plane_update()
2479 old_cdclk_state->actual.voltage_level); in intel_set_cdclk_pre_plane_update()
2482 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_pre_plane_update()
2488 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2497 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_set_cdclk_post_plane_update()
2504 if (!intel_cdclk_changed(&old_cdclk_state->actual, in intel_set_cdclk_post_plane_update()
2505 &new_cdclk_state->actual)) in intel_set_cdclk_post_plane_update()
2511 if (!new_cdclk_state->disable_pipes && in intel_set_cdclk_post_plane_update()
2512 new_cdclk_state->actual.cdclk < old_cdclk_state->actual.cdclk) in intel_set_cdclk_post_plane_update()
2513 pipe = new_cdclk_state->pipe; in intel_set_cdclk_post_plane_update()
2517 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed); in intel_set_cdclk_post_plane_update()
2519 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe); in intel_set_cdclk_post_plane_update()
2524 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_pixel_rate_to_cdclk()
2525 int pixel_rate = crtc_state->pixel_rate; in intel_pixel_rate_to_cdclk()
2534 else if (crtc_state->double_wide) in intel_pixel_rate_to_cdclk()
2542 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_planes_min_cdclk()
2543 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_planes_min_cdclk()
2547 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) in intel_planes_min_cdclk()
2548 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk); in intel_planes_min_cdclk()
2556 to_i915(crtc_state->uapi.crtc->dev); in intel_crtc_compute_min_cdclk()
2559 if (!crtc_state->hw.enable) in intel_crtc_compute_min_cdclk()
2574 crtc_state->has_audio && in intel_crtc_compute_min_cdclk()
2575 crtc_state->port_clock >= 540000 && in intel_crtc_compute_min_cdclk()
2576 crtc_state->lane_count == 4) { in intel_crtc_compute_min_cdclk()
2587 * According to BSpec, "The CD clock frequency must be at least twice in intel_crtc_compute_min_cdclk()
2588 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default. in intel_crtc_compute_min_cdclk()
2590 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9) in intel_crtc_compute_min_cdclk()
2594 * "For DP audio configuration, cdclk frequency shall be set to in intel_crtc_compute_min_cdclk()
2596 * DP Link Frequency(MHz) | Cdclk frequency(MHz) in intel_crtc_compute_min_cdclk()
2601 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio) in intel_crtc_compute_min_cdclk()
2602 min_cdclk = max(crtc_state->port_clock, min_cdclk); in intel_crtc_compute_min_cdclk()
2631 if (crtc_state->dsc.compression_enable) { in intel_crtc_compute_min_cdclk()
2635 DIV_ROUND_UP(crtc_state->pixel_rate, in intel_crtc_compute_min_cdclk()
2654 min_t(int, crtc_state->pixel_rate, in intel_crtc_compute_min_cdclk()
2655 dev_priv->display.cdclk.max_cdclk_freq)); in intel_crtc_compute_min_cdclk()
2663 struct intel_atomic_state *state = cdclk_state->base.state; in intel_compute_min_cdclk()
2664 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_compute_min_cdclk()
2678 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk) in intel_compute_min_cdclk()
2681 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk; in intel_compute_min_cdclk()
2683 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2692 if (cdclk_state->bw_min_cdclk != min_cdclk) { in intel_compute_min_cdclk()
2695 cdclk_state->bw_min_cdclk = min_cdclk; in intel_compute_min_cdclk()
2697 ret = intel_atomic_lock_global_state(&cdclk_state->base); in intel_compute_min_cdclk()
2703 min_cdclk = max(cdclk_state->force_min_cdclk, in intel_compute_min_cdclk()
2704 cdclk_state->bw_min_cdclk); in intel_compute_min_cdclk()
2706 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk); in intel_compute_min_cdclk()
2711 * CDCLK frequency is always high enough for audio. With a in intel_compute_min_cdclk()
2712 * single active pipe we can always change CDCLK frequency in intel_compute_min_cdclk()
2716 if (IS_GEMINILAKE(dev_priv) && cdclk_state->active_pipes && in intel_compute_min_cdclk()
2717 !is_power_of_2(cdclk_state->active_pipes)) in intel_compute_min_cdclk()
2720 if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) { in intel_compute_min_cdclk()
2721 drm_dbg_kms(&dev_priv->drm, in intel_compute_min_cdclk()
2723 min_cdclk, dev_priv->display.cdclk.max_cdclk_freq); in intel_compute_min_cdclk()
2724 return -EINVAL; in intel_compute_min_cdclk()
2745 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_compute_min_voltage_level()
2746 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_compute_min_voltage_level()
2756 if (crtc_state->hw.enable) in bxt_compute_min_voltage_level()
2757 min_voltage_level = crtc_state->min_voltage_level; in bxt_compute_min_voltage_level()
2761 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level) in bxt_compute_min_voltage_level()
2764 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level; in bxt_compute_min_voltage_level()
2766 ret = intel_atomic_lock_global_state(&cdclk_state->base); in bxt_compute_min_voltage_level()
2773 min_voltage_level = max(cdclk_state->min_voltage_level[pipe], in bxt_compute_min_voltage_level()
2781 struct intel_atomic_state *state = cdclk_state->base.state; in vlv_modeset_calc_cdclk()
2782 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in vlv_modeset_calc_cdclk()
2791 cdclk_state->logical.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2792 cdclk_state->logical.voltage_level = in vlv_modeset_calc_cdclk()
2795 if (!cdclk_state->active_pipes) { in vlv_modeset_calc_cdclk()
2796 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in vlv_modeset_calc_cdclk()
2798 cdclk_state->actual.cdclk = cdclk; in vlv_modeset_calc_cdclk()
2799 cdclk_state->actual.voltage_level = in vlv_modeset_calc_cdclk()
2802 cdclk_state->actual = cdclk_state->logical; in vlv_modeset_calc_cdclk()
2818 cdclk_state->logical.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2819 cdclk_state->logical.voltage_level = in bdw_modeset_calc_cdclk()
2822 if (!cdclk_state->active_pipes) { in bdw_modeset_calc_cdclk()
2823 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk); in bdw_modeset_calc_cdclk()
2825 cdclk_state->actual.cdclk = cdclk; in bdw_modeset_calc_cdclk()
2826 cdclk_state->actual.voltage_level = in bdw_modeset_calc_cdclk()
2829 cdclk_state->actual = cdclk_state->logical; in bdw_modeset_calc_cdclk()
2837 struct intel_atomic_state *state = cdclk_state->base.state; in skl_dpll0_vco()
2838 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in skl_dpll0_vco()
2843 vco = cdclk_state->logical.vco; in skl_dpll0_vco()
2845 vco = dev_priv->skl_preferred_vco_freq; in skl_dpll0_vco()
2848 if (!crtc_state->hw.enable) in skl_dpll0_vco()
2858 switch (crtc_state->port_clock / 2) { in skl_dpll0_vco()
2884 cdclk_state->logical.vco = vco; in skl_modeset_calc_cdclk()
2885 cdclk_state->logical.cdclk = cdclk; in skl_modeset_calc_cdclk()
2886 cdclk_state->logical.voltage_level = in skl_modeset_calc_cdclk()
2889 if (!cdclk_state->active_pipes) { in skl_modeset_calc_cdclk()
2890 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco); in skl_modeset_calc_cdclk()
2892 cdclk_state->actual.vco = vco; in skl_modeset_calc_cdclk()
2893 cdclk_state->actual.cdclk = cdclk; in skl_modeset_calc_cdclk()
2894 cdclk_state->actual.voltage_level = in skl_modeset_calc_cdclk()
2897 cdclk_state->actual = cdclk_state->logical; in skl_modeset_calc_cdclk()
2905 struct intel_atomic_state *state = cdclk_state->base.state; in bxt_modeset_calc_cdclk()
2906 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in bxt_modeset_calc_cdclk()
2920 cdclk_state->logical.vco = vco; in bxt_modeset_calc_cdclk()
2921 cdclk_state->logical.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2922 cdclk_state->logical.voltage_level = in bxt_modeset_calc_cdclk()
2926 if (!cdclk_state->active_pipes) { in bxt_modeset_calc_cdclk()
2927 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk); in bxt_modeset_calc_cdclk()
2930 cdclk_state->actual.vco = vco; in bxt_modeset_calc_cdclk()
2931 cdclk_state->actual.cdclk = cdclk; in bxt_modeset_calc_cdclk()
2932 cdclk_state->actual.voltage_level = in bxt_modeset_calc_cdclk()
2935 cdclk_state->actual = cdclk_state->logical; in bxt_modeset_calc_cdclk()
2946 * We can't change the cdclk frequency, but we still want to in fixed_modeset_calc_cdclk()
2947 * check that the required minimum frequency doesn't exceed in fixed_modeset_calc_cdclk()
2948 * the actual cdclk frequency. in fixed_modeset_calc_cdclk()
2961 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL); in intel_cdclk_duplicate_state()
2965 cdclk_state->pipe = INVALID_PIPE; in intel_cdclk_duplicate_state()
2966 cdclk_state->disable_pipes = false; in intel_cdclk_duplicate_state()
2968 return &cdclk_state->base; in intel_cdclk_duplicate_state()
2985 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_cdclk_state()
2988 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj); in intel_atomic_get_cdclk_state()
3024 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk) in intel_cdclk_atomic_check()
3036 return -ENOMEM; in intel_cdclk_init()
3038 intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj, in intel_cdclk_init()
3039 &cdclk_state->base, &intel_cdclk_funcs); in intel_cdclk_init()
3048 bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) != in intel_cdclk_need_serialize()
3049 hweight8(new_cdclk_state->active_pipes); in intel_cdclk_need_serialize()
3050 bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual, in intel_cdclk_need_serialize()
3051 &new_cdclk_state->actual); in intel_cdclk_need_serialize()
3061 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_modeset_calc_cdclk()
3073 new_cdclk_state->active_pipes = in intel_modeset_calc_cdclk()
3074 intel_calc_active_pipes(state, old_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
3085 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3088 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes || in intel_modeset_calc_cdclk()
3089 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk || in intel_modeset_calc_cdclk()
3090 intel_cdclk_changed(&old_cdclk_state->logical, in intel_modeset_calc_cdclk()
3091 &new_cdclk_state->logical)) { in intel_modeset_calc_cdclk()
3092 ret = intel_atomic_lock_global_state(&new_cdclk_state->base); in intel_modeset_calc_cdclk()
3099 if (is_power_of_2(new_cdclk_state->active_pipes) && in intel_modeset_calc_cdclk()
3101 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3102 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3106 pipe = ilog2(new_cdclk_state->active_pipes); in intel_modeset_calc_cdclk()
3109 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); in intel_modeset_calc_cdclk()
3118 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3119 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3120 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3123 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3124 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3125 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3128 &old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3129 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3130 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3133 new_cdclk_state->pipe = pipe; in intel_modeset_calc_cdclk()
3135 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3138 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual, in intel_modeset_calc_cdclk()
3139 &new_cdclk_state->actual)) { in intel_modeset_calc_cdclk()
3145 new_cdclk_state->disable_pipes = true; in intel_modeset_calc_cdclk()
3147 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3151 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3153 new_cdclk_state->logical.cdclk, in intel_modeset_calc_cdclk()
3154 new_cdclk_state->actual.cdclk); in intel_modeset_calc_cdclk()
3155 drm_dbg_kms(&dev_priv->drm, in intel_modeset_calc_cdclk()
3157 new_cdclk_state->logical.voltage_level, in intel_modeset_calc_cdclk()
3158 new_cdclk_state->actual.voltage_level); in intel_modeset_calc_cdclk()
3165 int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq; in intel_compute_max_dotclk()
3181 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3184 * Determine the maximum CDCLK frequency the platform supports, and also
3185 * derive the maximum dot clock frequency the maximum CDCLK frequency
3191 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3192 dev_priv->display.cdclk.max_cdclk_freq = 552000; in intel_update_max_cdclk()
3194 dev_priv->display.cdclk.max_cdclk_freq = 556800; in intel_update_max_cdclk()
3196 if (dev_priv->display.cdclk.hw.ref == 24000) in intel_update_max_cdclk()
3197 dev_priv->display.cdclk.max_cdclk_freq = 648000; in intel_update_max_cdclk()
3199 dev_priv->display.cdclk.max_cdclk_freq = 652800; in intel_update_max_cdclk()
3201 dev_priv->display.cdclk.max_cdclk_freq = 316800; in intel_update_max_cdclk()
3203 dev_priv->display.cdclk.max_cdclk_freq = 624000; in intel_update_max_cdclk()
3208 vco = dev_priv->skl_preferred_vco_freq; in intel_update_max_cdclk()
3209 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000); in intel_update_max_cdclk()
3225 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco); in intel_update_max_cdclk()
3234 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3236 dev_priv->display.cdclk.max_cdclk_freq = 450000; in intel_update_max_cdclk()
3238 dev_priv->display.cdclk.max_cdclk_freq = 540000; in intel_update_max_cdclk()
3240 dev_priv->display.cdclk.max_cdclk_freq = 675000; in intel_update_max_cdclk()
3242 dev_priv->display.cdclk.max_cdclk_freq = 320000; in intel_update_max_cdclk()
3244 dev_priv->display.cdclk.max_cdclk_freq = 400000; in intel_update_max_cdclk()
3247 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk; in intel_update_max_cdclk()
3250 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); in intel_update_max_cdclk()
3252 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n", in intel_update_max_cdclk()
3253 dev_priv->display.cdclk.max_cdclk_freq); in intel_update_max_cdclk()
3255 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n", in intel_update_max_cdclk()
3256 dev_priv->max_dotclk_freq); in intel_update_max_cdclk()
3260 * intel_update_cdclk - Determine the current CDCLK frequency
3263 * Determine the current CDCLK frequency.
3267 intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw); in intel_update_cdclk()
3270 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): in intel_update_cdclk()
3277 DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000)); in intel_update_cdclk()
3312 fraction) - 1); in cnp_rawclk()
3338 * hrawclock is 1/4 the FSB frequency in i9xx_hrawclk()
3341 * straps, not the actual FSB frequency. Some BIOSen in i9xx_hrawclk()
3343 * read out the actual FSB frequency but sadly we in i9xx_hrawclk()
3390 * intel_read_rawclk - Determine the current RAWCLK frequency
3393 * Determine the current RAWCLK frequency. RAWCLK is a fixed
3394 * frequency clock so this needs to done only once.
3426 struct drm_i915_private *i915 = m->private; in i915_cdclk_info_show()
3428 seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk); in i915_cdclk_info_show()
3429 seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq); in i915_cdclk_info_show()
3430 seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq); in i915_cdclk_info_show()
3439 struct drm_minor *minor = i915->drm.primary; in intel_cdclk_debugfs_register()
3441 debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root, in intel_cdclk_debugfs_register()
3589 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3595 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs; in intel_init_cdclk_hooks()
3596 dev_priv->display.cdclk.table = mtl_cdclk_table; in intel_init_cdclk_hooks()
3598 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3599 dev_priv->display.cdclk.table = dg2_cdclk_table; in intel_init_cdclk_hooks()
3601 /* Wa_22011320316:adl-p[a0] */ in intel_init_cdclk_hooks()
3603 dev_priv->display.cdclk.table = adlp_a_step_cdclk_table; in intel_init_cdclk_hooks()
3604 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3606 dev_priv->display.cdclk.table = rplu_cdclk_table; in intel_init_cdclk_hooks()
3607 dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; in intel_init_cdclk_hooks()
3609 dev_priv->display.cdclk.table = adlp_cdclk_table; in intel_init_cdclk_hooks()
3610 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3613 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3614 dev_priv->display.cdclk.table = rkl_cdclk_table; in intel_init_cdclk_hooks()
3616 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs; in intel_init_cdclk_hooks()
3617 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3619 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs; in intel_init_cdclk_hooks()
3620 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3622 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs; in intel_init_cdclk_hooks()
3623 dev_priv->display.cdclk.table = icl_cdclk_table; in intel_init_cdclk_hooks()
3625 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs; in intel_init_cdclk_hooks()
3627 dev_priv->display.cdclk.table = glk_cdclk_table; in intel_init_cdclk_hooks()
3629 dev_priv->display.cdclk.table = bxt_cdclk_table; in intel_init_cdclk_hooks()
3631 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs; in intel_init_cdclk_hooks()
3633 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs; in intel_init_cdclk_hooks()
3635 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs; in intel_init_cdclk_hooks()
3637 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs; in intel_init_cdclk_hooks()
3639 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs; in intel_init_cdclk_hooks()
3641 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3643 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs; in intel_init_cdclk_hooks()
3645 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs; in intel_init_cdclk_hooks()
3647 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3649 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs; in intel_init_cdclk_hooks()
3651 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3653 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs; in intel_init_cdclk_hooks()
3655 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs; in intel_init_cdclk_hooks()
3657 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs; in intel_init_cdclk_hooks()
3659 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs; in intel_init_cdclk_hooks()
3661 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs; in intel_init_cdclk_hooks()
3663 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs; in intel_init_cdclk_hooks()
3665 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs; in intel_init_cdclk_hooks()
3667 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs; in intel_init_cdclk_hooks()
3669 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs; in intel_init_cdclk_hooks()
3671 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()
3674 if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk, in intel_init_cdclk_hooks()
3676 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs; in intel_init_cdclk_hooks()