Lines Matching defs:mipi_config

98 struct mipi_config {  struct
99 	u16 panel_id;
102 	u32 enable_dithering:1;
103 	u32 rsvd1:1;
104 	u32 is_bridge:1;
106 	u32 panel_arch_type:2;
107 	u32 is_cmd_mode:1;
112 	u32 video_transfer_mode:2;
114 	u32 cabc_supported:1;
117 	u32 pwm_blc:1;
124 	u32 videomode_color_format:4;
131 	u32 rotation:2;
132 	u32 bta_enabled:1;
133 	u32 rsvd2:15;
139 	u16 dual_link:2;
140 	u16 lane_cnt:2;
141 	u16 pixel_overlap:3;
142 	u16 rgb_flip:1;
146 	u16 dl_dcs_cabc_ports:2;
147 	u16 dl_dcs_backlight_ports:2;
148 	u16 rsvd3:4;
150 	u16 rsvd4;
152 	u8 rsvd5;
153 	u32 target_burst_mode_freq;
154 	u32 dsi_ddr_clk;
155 	u32 bridge_ref_clk;
160 	u8 byte_clk_sel:2;
162 	u8 rsvd6:6;
165 	u16 dphy_param_valid:1;
166 	u16 eot_pkt_disabled:1;
167 	u16 enable_clk_stop:1;
168 	u16 rsvd7:13;
170 	u32 hs_tx_timeout;
171 	u32 lp_rx_timeout;
172 	u32 turn_around_timeout;
173 	u32 device_reset_timer;
174 	u32 master_init_timer;
175 	u32 dbi_bw_timer;
176 	u32 lp_byte_clk_val;
179 	u32 prepare_cnt:6;
180 	u32 rsvd8:2;
181 	u32 clk_zero_cnt:8;
182 	u32 trail_cnt:5;
183 	u32 rsvd9:3;
184 	u32 exit_zero_cnt:6;
185 	u32 rsvd10:2;
187 	u32 clk_lane_switch_cnt;
188 	u32 hl_switch_cnt;
190 	u32 rsvd11[6];
193 	u8 tclk_miss;
194 	u8 tclk_post;
195 	u8 rsvd12;
196 	u8 tclk_pre;
197 	u8 tclk_prepare;
198 	u8 tclk_settle;
199 	u8 tclk_term_enable;
200 	u8 tclk_trail;
201 	u16 tclk_prepare_clkzero;
202 	u8 rsvd13;
203 	u8 td_term_enable;
204 	u8 teot;
205 	u8 ths_exit;
206 	u8 ths_prepare;
207 	u16 ths_prepare_hszero;
208 	u8 rsvd14;
209 	u8 ths_settle;
210 	u8 ths_skip;
211 	u8 ths_trail;
212 	u8 tinit;
213 	u8 tlpx;
214 	u8 rsvd15[3];
217 	u8 panel_enable;
218 	u8 bl_enable;
219 	u8 pwm_enable;
220 	u8 reset_r_n;
221 	u8 pwr_down_r;
222 	u8 stdby_r_n;