Lines Matching full:plane
25 * DOC: atomic plane helpers
27 * The functions here are used by the atomic plane helper functions to
28 * implement legacy plane updates (i.e., drm_plane->update_plane() and
29 * drm_plane->disable_plane()). This allows plane updates to use the
30 * atomic state infrastructure and perform plane updates as separate
51 struct intel_plane *plane) in intel_plane_state_reset() argument
55 __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base); in intel_plane_state_reset()
63 struct intel_plane *plane; in intel_plane_alloc() local
65 plane = kzalloc(sizeof(*plane), GFP_KERNEL); in intel_plane_alloc()
66 if (!plane) in intel_plane_alloc()
71 kfree(plane); in intel_plane_alloc()
75 intel_plane_state_reset(plane_state, plane); in intel_plane_alloc()
77 plane->base.state = &plane_state->uapi; in intel_plane_alloc()
79 return plane; in intel_plane_alloc()
82 void intel_plane_free(struct intel_plane *plane) in intel_plane_free() argument
84 intel_plane_destroy_state(&plane->base, plane->base.state); in intel_plane_free()
85 kfree(plane); in intel_plane_free()
89 * intel_plane_duplicate_state - duplicate plane state
90 * @plane: drm plane
92 * Allocates and returns a copy of the plane state (both common and
93 * Intel-specific) for the specified plane.
95 * Returns: The newly allocated plane state, or NULL on failure.
98 intel_plane_duplicate_state(struct drm_plane *plane) in intel_plane_duplicate_state() argument
102 intel_state = to_intel_plane_state(plane->state); in intel_plane_duplicate_state()
108 __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi); in intel_plane_duplicate_state()
122 * intel_plane_destroy_state - destroy plane state
123 * @plane: drm plane
126 * Destroys the plane state (both common and Intel-specific) for the
127 * specified plane.
130 intel_plane_destroy_state(struct drm_plane *plane, in intel_plane_destroy_state() argument
135 drm_WARN_ON(plane->dev, plane_state->ggtt_vma); in intel_plane_destroy_state()
136 drm_WARN_ON(plane->dev, plane_state->dpt_vma); in intel_plane_destroy_state()
167 * Note we don't check for plane visibility here as in intel_plane_pixel_rate()
198 struct intel_plane *plane) in use_min_ddb() argument
200 struct drm_i915_private *i915 = to_i915(plane->base.dev); in use_min_ddb()
204 plane->async_flip; in use_min_ddb()
212 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_relative_data_rate() local
217 if (plane->id == PLANE_CURSOR) in intel_plane_relative_data_rate()
224 * We calculate extra ddb based on ratio plane rate/total data rate in intel_plane_relative_data_rate()
225 * in case, in some cases we should not allocate extra ddb for the plane, in intel_plane_relative_data_rate()
228 if (use_min_ddb(crtc_state, plane)) in intel_plane_relative_data_rate()
233 * the 90/270 degree plane rotation cases (to match the in intel_plane_relative_data_rate()
239 /* UV plane does 1/2 pixel sub-sampling */ in intel_plane_relative_data_rate()
253 struct intel_plane *plane, in intel_plane_calc_min_cdclk() argument
256 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_plane_calc_min_cdclk()
258 intel_atomic_get_new_plane_state(state, plane); in intel_plane_calc_min_cdclk()
264 if (!plane_state->uapi.visible || !plane->min_cdclk) in intel_plane_calc_min_cdclk()
270 new_crtc_state->min_cdclk[plane->id] = in intel_plane_calc_min_cdclk()
271 plane->min_cdclk(new_crtc_state, plane_state); in intel_plane_calc_min_cdclk()
275 * the min cdclk for the plane doesn't increase. in intel_plane_calc_min_cdclk()
277 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
281 if (new_crtc_state->min_cdclk[plane->id] <= in intel_plane_calc_min_cdclk()
282 old_crtc_state->min_cdclk[plane->id]) in intel_plane_calc_min_cdclk()
293 * Ie. we only ever increase the cdclk due to plane in intel_plane_calc_min_cdclk()
297 if (new_crtc_state->min_cdclk[plane->id] <= in intel_plane_calc_min_cdclk()
302 "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n", in intel_plane_calc_min_cdclk()
303 plane->base.base.id, plane->base.name, in intel_plane_calc_min_cdclk()
304 new_crtc_state->min_cdclk[plane->id], in intel_plane_calc_min_cdclk()
330 * the plane is logically enabled on the uapi level. in intel_plane_copy_uapi_to_hw_state()
365 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); in intel_plane_set_invisible() local
367 crtc_state->active_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
368 crtc_state->scaled_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
369 crtc_state->nv12_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
370 crtc_state->c8_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
371 crtc_state->async_flip_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
372 crtc_state->data_rate[plane->id] = 0; in intel_plane_set_invisible()
373 crtc_state->data_rate_y[plane->id] = 0; in intel_plane_set_invisible()
374 crtc_state->rel_data_rate[plane->id] = 0; in intel_plane_set_invisible()
375 crtc_state->rel_data_rate_y[plane->id] = 0; in intel_plane_set_invisible()
376 crtc_state->min_cdclk[plane->id] = 0; in intel_plane_set_invisible()
413 static bool intel_plane_do_async_flip(struct intel_plane *plane, in intel_plane_do_async_flip() argument
417 struct drm_i915_private *i915 = to_i915(plane->base.dev); in intel_plane_do_async_flip()
419 if (!plane->async_flip) in intel_plane_do_async_flip()
439 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); in i9xx_must_disable_cxsr() local
446 if (plane->id == PLANE_CURSOR) in i9xx_must_disable_cxsr()
453 /* Must disable CxSR around plane enable/disable */ in i9xx_must_disable_cxsr()
461 * Most plane control register updates are blocked while in CxSR. in i9xx_must_disable_cxsr()
463 * Tiling mode is one exception where the primary plane can in i9xx_must_disable_cxsr()
468 if (plane->id == PLANE_PRIMARY) { in i9xx_must_disable_cxsr()
482 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); in intel_plane_atomic_calc_changes() local
490 if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { in intel_plane_atomic_calc_changes()
509 * per-plane wm computation to the .check_plane() hook, and in intel_plane_atomic_calc_changes()
524 "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", in intel_plane_atomic_calc_changes()
526 plane->base.base.id, plane->base.name, in intel_plane_atomic_calc_changes()
545 new_crtc_state->fb_bits |= plane->frontbuffer_bit; in intel_plane_atomic_calc_changes()
555 * plane will be internally buffered and delayed while Big FIFO in intel_plane_atomic_calc_changes()
582 * plane, not only sprite plane. in intel_plane_atomic_calc_changes()
584 if (plane->id != PLANE_CURSOR && in intel_plane_atomic_calc_changes()
591 if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) { in intel_plane_atomic_calc_changes()
593 new_crtc_state->async_flip_planes |= BIT(plane->id); in intel_plane_atomic_calc_changes()
604 struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane); in intel_plane_atomic_check_with_state() local
609 new_crtc_state->enabled_planes &= ~BIT(plane->id); in intel_plane_atomic_check_with_state()
614 ret = plane->check_plane(new_crtc_state, new_plane_state); in intel_plane_atomic_check_with_state()
619 new_crtc_state->enabled_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
623 new_crtc_state->active_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
627 new_crtc_state->scaled_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
631 new_crtc_state->nv12_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
635 new_crtc_state->c8_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
638 new_crtc_state->update_planes |= BIT(plane->id); in intel_plane_atomic_check_with_state()
642 new_crtc_state->data_rate_y[plane->id] = in intel_plane_atomic_check_with_state()
644 new_crtc_state->data_rate[plane->id] = in intel_plane_atomic_check_with_state()
647 new_crtc_state->rel_data_rate_y[plane->id] = in intel_plane_atomic_check_with_state()
650 new_crtc_state->rel_data_rate[plane->id] = in intel_plane_atomic_check_with_state()
654 new_crtc_state->data_rate[plane->id] = in intel_plane_atomic_check_with_state()
657 new_crtc_state->rel_data_rate[plane->id] = in intel_plane_atomic_check_with_state()
670 struct intel_plane *plane; in intel_crtc_get_plane() local
672 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { in intel_crtc_get_plane()
673 if (plane->id == plane_id) in intel_crtc_get_plane()
674 return plane; in intel_crtc_get_plane()
681 struct intel_plane *plane) in intel_plane_atomic_check() argument
685 intel_atomic_get_new_plane_state(state, plane); in intel_plane_atomic_check()
687 intel_atomic_get_old_plane_state(state, plane); in intel_plane_atomic_check()
689 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe); in intel_plane_atomic_check()
699 intel_crtc_get_plane(master_crtc, plane->id); in intel_plane_atomic_check()
731 struct intel_plane *plane; in skl_next_plane_to_commit() local
737 for_each_new_intel_plane_in_state(state, plane, plane_state, i) { in skl_next_plane_to_commit()
738 enum plane_id plane_id = plane->id; in skl_next_plane_to_commit()
740 if (crtc->pipe != plane->pipe || in skl_next_plane_to_commit()
754 return plane; in skl_next_plane_to_commit()
763 void intel_plane_update_noarm(struct intel_plane *plane, in intel_plane_update_noarm() argument
769 trace_intel_plane_update_noarm(plane, crtc); in intel_plane_update_noarm()
771 if (plane->update_noarm) in intel_plane_update_noarm()
772 plane->update_noarm(plane, crtc_state, plane_state); in intel_plane_update_noarm()
775 void intel_plane_update_arm(struct intel_plane *plane, in intel_plane_update_arm() argument
781 trace_intel_plane_update_arm(plane, crtc); in intel_plane_update_arm()
783 if (crtc_state->do_async_flip && plane->async_flip) in intel_plane_update_arm()
784 plane->async_flip(plane, crtc_state, plane_state, true); in intel_plane_update_arm()
786 plane->update_arm(plane, crtc_state, plane_state); in intel_plane_update_arm()
789 void intel_plane_disable_arm(struct intel_plane *plane, in intel_plane_disable_arm() argument
794 trace_intel_plane_disable_arm(plane, crtc); in intel_plane_disable_arm()
795 plane->disable_arm(plane, crtc_state); in intel_plane_disable_arm()
805 struct intel_plane *plane; in intel_crtc_planes_update_noarm() local
815 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { in intel_crtc_planes_update_noarm()
816 if (crtc->pipe != plane->pipe || in intel_crtc_planes_update_noarm()
817 !(update_mask & BIT(plane->id))) in intel_crtc_planes_update_noarm()
823 intel_plane_update_noarm(plane, new_crtc_state, new_plane_state); in intel_crtc_planes_update_noarm()
837 struct intel_plane *plane; in skl_crtc_planes_update_arm() local
844 while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) { in skl_crtc_planes_update_arm()
846 intel_atomic_get_new_plane_state(state, plane); in skl_crtc_planes_update_arm()
854 intel_plane_update_arm(plane, new_crtc_state, new_plane_state); in skl_crtc_planes_update_arm()
856 intel_plane_disable_arm(plane, new_crtc_state); in skl_crtc_planes_update_arm()
867 struct intel_plane *plane; in i9xx_crtc_planes_update_arm() local
870 for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) { in i9xx_crtc_planes_update_arm()
871 if (crtc->pipe != plane->pipe || in i9xx_crtc_planes_update_arm()
872 !(update_mask & BIT(plane->id))) in i9xx_crtc_planes_update_arm()
880 intel_plane_update_arm(plane, new_crtc_state, new_plane_state); in i9xx_crtc_planes_update_arm()
882 intel_plane_disable_arm(plane, new_crtc_state); in i9xx_crtc_planes_update_arm()
902 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in intel_atomic_plane_check_clipping()
921 drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n"); in intel_atomic_plane_check_clipping()
937 drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n"); in intel_atomic_plane_check_clipping()
943 /* final plane coordinates will be relative to the plane's pipe */ in intel_atomic_plane_check_clipping()
951 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); in intel_plane_check_src_coordinates()
1008 * intel_prepare_plane_fb - Prepare fb for usage on plane
1009 * @_plane: drm plane to prepare for
1010 * @_new_plane_state: the plane state being prepared
1012 * Prepares a framebuffer for usage on a display plane. Generally this
1024 struct intel_plane *plane = to_intel_plane(_plane); in intel_prepare_plane_fb() local
1029 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); in intel_prepare_plane_fb()
1031 intel_atomic_get_old_plane_state(state, plane); in intel_prepare_plane_fb()
1125 * intel_cleanup_plane_fb - Cleans up an fb after plane use
1126 * @plane: drm plane to clean up for
1129 * Cleans up a framebuffer that has just been removed from a plane.
1132 intel_cleanup_plane_fb(struct drm_plane *plane, in intel_cleanup_plane_fb() argument
1139 struct drm_i915_private *dev_priv = to_i915(plane->dev); in intel_cleanup_plane_fb()
1156 void intel_plane_helper_add(struct intel_plane *plane) in intel_plane_helper_add() argument
1158 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); in intel_plane_helper_add()