Lines Matching +full:10 +full:base +full:- +full:te
71 drm_err(&dev_priv->drm, "DSI header credits not released\n"); in wait_for_header_credits()
83 drm_err(&dev_priv->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
100 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in wait_for_cmds_dispatched_to_panel()
108 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
115 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
116 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
117 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
118 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
121 drm_err(&dev_priv->drm, in wait_for_cmds_dispatched_to_panel()
126 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
132 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
136 drm_err(&dev_priv->drm, "LPTX bit not cleared\n"); in wait_for_cmds_dispatched_to_panel()
143 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_payld()
144 struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev); in dsi_send_pkt_payld()
145 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_payld()
146 const u8 *data = packet->payload; in dsi_send_pkt_payld()
147 u32 len = packet->payload_length; in dsi_send_pkt_payld()
152 drm_err(&i915->drm, "payload size exceeds max queue limit\n"); in dsi_send_pkt_payld()
153 return -EINVAL; in dsi_send_pkt_payld()
160 return -EBUSY; in dsi_send_pkt_payld()
162 for (j = 0; j < min_t(u32, len - i, 4); j++) in dsi_send_pkt_payld()
175 struct intel_dsi *intel_dsi = host->intel_dsi; in dsi_send_pkt_hdr()
176 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); in dsi_send_pkt_hdr()
177 enum transcoder dsi_trans = dsi_port_to_transcoder(host->port); in dsi_send_pkt_hdr()
181 return -EBUSY; in dsi_send_pkt_hdr()
185 if (packet->payload) in dsi_send_pkt_hdr()
198 tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT); in dsi_send_pkt_hdr()
199 tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT); in dsi_send_pkt_hdr()
200 tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT); in dsi_send_pkt_hdr()
201 tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT); in dsi_send_pkt_hdr()
209 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in icl_dsi_frame_update()
210 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in icl_dsi_frame_update()
214 mode_flags = crtc_state->mode_flags; in icl_dsi_frame_update()
233 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in dsi_program_swing_and_deemphasis()
239 for_each_dsi_phy(phy, intel_dsi->phys) { in dsi_program_swing_and_deemphasis()
241 * Program voltage swing and pre-emphasis level values as per in dsi_program_swing_and_deemphasis()
279 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in configure_dual_link_mode()
286 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in configure_dual_link_mode()
288 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe); in configure_dual_link_mode()
289 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe); in configure_dual_link_mode()
298 dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap); in configure_dual_link_mode()
300 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in configure_dual_link_mode()
302 &pipe_config->hw.adjusted_mode; in configure_dual_link_mode()
303 u16 hactive = adjusted_mode->crtc_hdisplay; in configure_dual_link_mode()
307 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap; in configure_dual_link_mode()
310 drm_err(&dev_priv->drm, in configure_dual_link_mode()
332 if (crtc_state->dsc.compression_enable) in afe_clk()
333 bpp = crtc_state->dsc.compressed_bpp; in afe_clk()
335 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in afe_clk()
337 return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count); in afe_clk()
343 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_program_esc_clk_div()
356 esc_clk_div_m_phy = (act_word_clk - 1) / 2; in gen11_dsi_program_esc_clk_div()
361 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
367 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
374 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_program_esc_clk_div()
387 for_each_dsi_port(port, intel_dsi->ports) { in get_dsi_io_power_domains()
388 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]); in get_dsi_io_power_domains()
389 intel_dsi->io_wakeref[port] = in get_dsi_io_power_domains()
399 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_enable_io_power()
403 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_enable_io_power()
412 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_power_up_lanes()
416 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_power_up_lanes()
418 intel_dsi->lane_count, false); in gen11_dsi_power_up_lanes()
423 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_config_phy_lanes_sequence()
430 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
438 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_config_phy_lanes_sequence()
465 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_voltage_swing_program_seq()
471 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
483 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_voltage_swing_program_seq()
487 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
494 /* Program swing and de-emphasis */ in gen11_dsi_voltage_swing_program_seq()
498 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_voltage_swing_program_seq()
508 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_enable_ddi_buffer()
512 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_ddi_buffer()
518 drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n", in gen11_dsi_enable_ddi_buffer()
527 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_setup_dphy_timings()
533 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
535 intel_dsi->dphy_reg); in gen11_dsi_setup_dphy_timings()
538 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
540 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_dphy_timings()
550 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_dphy_timings()
558 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_setup_dphy_timings()
568 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_setup_timings()
572 /* Program T-INIT master registers */ in gen11_dsi_setup_timings()
573 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
575 DSI_T_INIT_MASTER_MASK, intel_dsi->init_count); in gen11_dsi_setup_timings()
578 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
580 intel_dsi->dphy_reg); in gen11_dsi_setup_timings()
583 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_setup_timings()
585 intel_dsi->dphy_data_lane_reg); in gen11_dsi_setup_timings()
590 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_timings()
601 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_gate_clocks()
606 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_gate_clocks()
608 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_gate_clocks()
612 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_gate_clocks()
617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_ungate_clocks()
622 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_ungate_clocks()
624 for_each_dsi_phy(phy, intel_dsi->phys) in gen11_dsi_ungate_clocks()
628 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_ungate_clocks()
633 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_is_clock_enabled()
641 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_is_clock_enabled()
652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_map_pll()
654 struct intel_shared_dpll *pll = crtc_state->shared_dpll; in gen11_dsi_map_pll()
658 mutex_lock(&dev_priv->display.dpll.lock); in gen11_dsi_map_pll()
661 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
663 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy); in gen11_dsi_map_pll()
667 for_each_dsi_phy(phy, intel_dsi->phys) { in gen11_dsi_map_pll()
674 mutex_unlock(&dev_priv->display.dpll.lock); in gen11_dsi_map_pll()
681 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_configure_transcoder()
683 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_configure_transcoder()
684 enum pipe pipe = crtc->pipe; in gen11_dsi_configure_transcoder()
689 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
693 if (intel_dsi->eotp_pkt) in gen11_dsi_configure_transcoder()
706 if (intel_dsi->clock_stop) in gen11_dsi_configure_transcoder()
720 if (intel_dsi->bgr_enabled) in gen11_dsi_configure_transcoder()
725 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
728 switch (intel_dsi->pixel_format) { in gen11_dsi_configure_transcoder()
730 MISSING_CASE(intel_dsi->pixel_format); in gen11_dsi_configure_transcoder()
755 switch (intel_dsi->video_mode) { in gen11_dsi_configure_transcoder()
757 MISSING_CASE(intel_dsi->video_mode); in gen11_dsi_configure_transcoder()
770 * in TE GATE mode, TE comes from GPIO in gen11_dsi_configure_transcoder()
784 if (intel_dsi->dual_link) { in gen11_dsi_configure_transcoder()
785 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
795 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
801 tmp |= TRANS_DDI_PORT_WIDTH(intel_dsi->lane_count); in gen11_dsi_configure_transcoder()
829 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_configure_transcoder()
833 drm_err(&dev_priv->drm, "DSI link not ready\n"); in gen11_dsi_configure_transcoder()
841 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_set_transcoder_timings()
844 &crtc_state->hw.adjusted_mode; in gen11_dsi_set_transcoder_timings()
859 * non-compressed link speeds, and simplifies down to the ratio between in gen11_dsi_set_transcoder_timings()
860 * compressed and non-compressed bpp. in gen11_dsi_set_transcoder_timings()
862 if (crtc_state->dsc.compression_enable) { in gen11_dsi_set_transcoder_timings()
863 mul = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
864 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
867 hactive = adjusted_mode->crtc_hdisplay; in gen11_dsi_set_transcoder_timings()
870 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_set_transcoder_timings()
874 hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_set_transcoder_timings()
875 hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_set_transcoder_timings()
876 hsync_size = hsync_end - hsync_start; in gen11_dsi_set_transcoder_timings()
877 hback_porch = (adjusted_mode->crtc_htotal - in gen11_dsi_set_transcoder_timings()
878 adjusted_mode->crtc_hsync_end); in gen11_dsi_set_transcoder_timings()
879 vactive = adjusted_mode->crtc_vdisplay; in gen11_dsi_set_transcoder_timings()
882 vtotal = adjusted_mode->crtc_vtotal; in gen11_dsi_set_transcoder_timings()
886 if (crtc_state->dsc.compression_enable) in gen11_dsi_set_transcoder_timings()
887 bpp = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
889 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_set_transcoder_timings()
892 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count); in gen11_dsi_set_transcoder_timings()
895 vsync_start = adjusted_mode->crtc_vsync_start; in gen11_dsi_set_transcoder_timings()
896 vsync_end = adjusted_mode->crtc_vsync_end; in gen11_dsi_set_transcoder_timings()
897 vsync_shift = hsync_start - htotal / 2; in gen11_dsi_set_transcoder_timings()
899 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
901 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_set_transcoder_timings()
902 hactive += intel_dsi->pixel_overlap; in gen11_dsi_set_transcoder_timings()
907 if (adjusted_mode->crtc_hdisplay < 256) in gen11_dsi_set_transcoder_timings()
908 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n"); in gen11_dsi_set_transcoder_timings()
911 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0) in gen11_dsi_set_transcoder_timings()
912 drm_err(&dev_priv->drm, in gen11_dsi_set_transcoder_timings()
916 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
919 HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); in gen11_dsi_set_transcoder_timings()
924 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) { in gen11_dsi_set_transcoder_timings()
927 drm_err(&dev_priv->drm, in gen11_dsi_set_transcoder_timings()
932 drm_err(&dev_priv->drm, "hback porch < 16 pixels\n"); in gen11_dsi_set_transcoder_timings()
934 if (intel_dsi->dual_link) { in gen11_dsi_set_transcoder_timings()
939 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
942 HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); in gen11_dsi_set_transcoder_timings()
947 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
951 * non-interlaced info from VBT is not saved inside in gen11_dsi_set_transcoder_timings()
956 VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); in gen11_dsi_set_transcoder_timings()
960 drm_err(&dev_priv->drm, "Invalid vsync_end value\n"); in gen11_dsi_set_transcoder_timings()
963 drm_err(&dev_priv->drm, "vsync_start less than vactive\n"); in gen11_dsi_set_transcoder_timings()
967 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
970 VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); in gen11_dsi_set_transcoder_timings()
981 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
995 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_set_transcoder_timings()
998 VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); in gen11_dsi_set_transcoder_timings()
1005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_enable_transcoder()
1010 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_enable_transcoder()
1016 TRANSCONF_STATE_ENABLE, 10)) in gen11_dsi_enable_transcoder()
1017 drm_err(&dev_priv->drm, in gen11_dsi_enable_transcoder()
1025 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_setup_timeouts()
1034 * UI (nsec) = (10^6)/Bitrate in gen11_dsi_setup_timeouts()
1035 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate in gen11_dsi_setup_timeouts()
1040 hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul, in gen11_dsi_setup_timeouts()
1042 lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor); in gen11_dsi_setup_timeouts()
1043 ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor); in gen11_dsi_setup_timeouts()
1045 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_setup_timeouts()
1072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_config_util_pin()
1077 * used as TE i/p for DSI0, in gen11_dsi_config_util_pin()
1078 * for dual link/DSI1 TE is from slave DSI1 in gen11_dsi_config_util_pin()
1081 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) in gen11_dsi_config_util_pin()
1102 /* step 4b: configure lane sequencing of the Combo-PHY transmitters */ in gen11_dsi_enable_port_and_phy()
1108 /* setup D-PHY timings */ in gen11_dsi_enable_port_and_phy()
1130 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_powerup_panel()
1139 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_powerup_panel()
1150 dsi = intel_dsi->dsi_hosts[port]->device; in gen11_dsi_powerup_panel()
1153 drm_err(&dev_priv->drm, in gen11_dsi_powerup_panel()
1173 msleep(intel_dsi->panel_on_delay); in gen11_dsi_pre_pll_enable()
1213 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_apply_kvmr_pipe_a_wa()
1222 * Wa_16012360555:adl-p
1229 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adlp_set_lp_hs_wakeup_gb()
1234 for_each_dsi_port(port, intel_dsi->ports) in adlp_set_lp_hs_wakeup_gb()
1247 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in gen11_dsi_enable()
1250 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true); in gen11_dsi_enable()
1252 /* Wa_16012360555:adl-p */ in gen11_dsi_enable()
1269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_transcoder()
1274 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_transcoder()
1283 drm_err(&dev_priv->drm, in gen11_dsi_disable_transcoder()
1300 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_deconfigure_trancoder()
1308 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_deconfigure_trancoder()
1314 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1323 10)) in gen11_dsi_deconfigure_trancoder()
1324 drm_err(&dev_priv->drm, "DSI link not in ULPS\n"); in gen11_dsi_deconfigure_trancoder()
1328 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1335 if (intel_dsi->dual_link) { in gen11_dsi_deconfigure_trancoder()
1336 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_deconfigure_trancoder()
1346 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_port()
1351 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_port()
1357 drm_err(&dev_priv->drm, in gen11_dsi_disable_port()
1366 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_disable_io_power()
1370 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_disable_io_power()
1373 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]); in gen11_dsi_disable_io_power()
1382 for_each_dsi_port(port, intel_dsi->ports) in gen11_dsi_disable_io_power()
1405 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in gen11_dsi_post_disable()
1413 icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false); in gen11_dsi_post_disable()
1434 msleep(intel_dsi->panel_off_delay); in gen11_dsi_post_disable()
1437 intel_dsi->panel_power_off_time = ktime_get_boottime(); in gen11_dsi_post_disable()
1443 struct drm_i915_private *i915 = to_i915(connector->dev); in gen11_dsi_mode_valid()
1459 &pipe_config->hw.adjusted_mode; in gen11_dsi_get_timings()
1461 if (pipe_config->dsc.compressed_bpp) { in gen11_dsi_get_timings()
1462 int div = pipe_config->dsc.compressed_bpp; in gen11_dsi_get_timings()
1463 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in gen11_dsi_get_timings()
1465 adjusted_mode->crtc_htotal = in gen11_dsi_get_timings()
1466 DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div); in gen11_dsi_get_timings()
1467 adjusted_mode->crtc_hsync_start = in gen11_dsi_get_timings()
1468 DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div); in gen11_dsi_get_timings()
1469 adjusted_mode->crtc_hsync_end = in gen11_dsi_get_timings()
1470 DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div); in gen11_dsi_get_timings()
1473 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1474 adjusted_mode->crtc_hdisplay *= 2; in gen11_dsi_get_timings()
1475 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in gen11_dsi_get_timings()
1476 adjusted_mode->crtc_hdisplay -= in gen11_dsi_get_timings()
1477 intel_dsi->pixel_overlap; in gen11_dsi_get_timings()
1478 adjusted_mode->crtc_htotal *= 2; in gen11_dsi_get_timings()
1480 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in gen11_dsi_get_timings()
1481 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in gen11_dsi_get_timings()
1483 if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) { in gen11_dsi_get_timings()
1484 if (intel_dsi->dual_link) { in gen11_dsi_get_timings()
1485 adjusted_mode->crtc_hsync_start *= 2; in gen11_dsi_get_timings()
1486 adjusted_mode->crtc_hsync_end *= 2; in gen11_dsi_get_timings()
1489 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in gen11_dsi_get_timings()
1490 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in gen11_dsi_get_timings()
1495 struct drm_device *dev = intel_dsi->base.base.dev; in gen11_dsi_is_periodic_cmd_mode()
1500 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_is_periodic_cmd_mode()
1512 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1513 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 | in gen11_dsi_get_cmd_mode_config()
1515 else if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_get_cmd_mode_config()
1516 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1; in gen11_dsi_get_cmd_mode_config()
1518 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0; in gen11_dsi_get_cmd_mode_config()
1524 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in gen11_dsi_get_config()
1529 pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk; in gen11_dsi_get_config()
1530 if (intel_dsi->dual_link) in gen11_dsi_get_config()
1531 pipe_config->hw.adjusted_mode.crtc_clock *= 2; in gen11_dsi_get_config()
1534 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in gen11_dsi_get_config()
1535 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in gen11_dsi_get_config()
1537 /* Get the details on which TE should be enabled */ in gen11_dsi_get_config()
1542 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE; in gen11_dsi_get_config()
1548 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_sync_state()
1555 intel_crtc = to_intel_crtc(crtc_state->uapi.crtc); in gen11_dsi_sync_state()
1556 pipe = intel_crtc->pipe; in gen11_dsi_sync_state()
1561 drm_dbg_kms(&dev_priv->drm, in gen11_dsi_sync_state()
1563 encoder->base.base.id, in gen11_dsi_sync_state()
1564 encoder->base.name); in gen11_dsi_sync_state()
1570 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_dsc_compute_config()
1571 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; in gen11_dsi_dsc_compute_config()
1572 int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10; in gen11_dsi_dsc_compute_config()
1580 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1581 return -EINVAL; in gen11_dsi_dsc_compute_config()
1584 if (crtc_state->dsc.slice_count > 1) in gen11_dsi_dsc_compute_config()
1585 crtc_state->dsc.dsc_split = true; in gen11_dsi_dsc_compute_config()
1588 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; in gen11_dsi_dsc_compute_config()
1590 vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay; in gen11_dsi_dsc_compute_config()
1597 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable); in gen11_dsi_dsc_compute_config()
1598 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422); in gen11_dsi_dsc_compute_config()
1599 drm_WARN_ON(&dev_priv->drm, in gen11_dsi_dsc_compute_config()
1600 vdsc_cfg->pic_width % vdsc_cfg->slice_width); in gen11_dsi_dsc_compute_config()
1601 drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8); in gen11_dsi_dsc_compute_config()
1602 drm_WARN_ON(&dev_priv->drm, in gen11_dsi_dsc_compute_config()
1603 vdsc_cfg->pic_height % vdsc_cfg->slice_height); in gen11_dsi_dsc_compute_config()
1609 crtc_state->dsc.compression_enable = true; in gen11_dsi_dsc_compute_config()
1618 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen11_dsi_compute_config()
1620 base); in gen11_dsi_compute_config()
1621 struct intel_connector *intel_connector = intel_dsi->attached_connector; in gen11_dsi_compute_config()
1623 &pipe_config->hw.adjusted_mode; in gen11_dsi_compute_config()
1626 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in gen11_dsi_compute_config()
1627 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in gen11_dsi_compute_config()
1637 adjusted_mode->flags = 0; in gen11_dsi_compute_config()
1640 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_compute_config()
1641 pipe_config->cpu_transcoder = TRANSCODER_DSI_1; in gen11_dsi_compute_config()
1643 pipe_config->cpu_transcoder = TRANSCODER_DSI_0; in gen11_dsi_compute_config()
1645 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in gen11_dsi_compute_config()
1646 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1648 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
1650 pipe_config->clock_set = true; in gen11_dsi_compute_config()
1653 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n"); in gen11_dsi_compute_config()
1655 pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5; in gen11_dsi_compute_config()
1658 * In case of TE GATE cmd mode, we in gen11_dsi_compute_config()
1659 * receive TE from the slave if in gen11_dsi_compute_config()
1671 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen11_dsi_get_power_domains()
1680 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in gen11_dsi_get_hw_state()
1689 encoder->power_domain); in gen11_dsi_get_hw_state()
1693 for_each_dsi_port(port, intel_dsi->ports) { in gen11_dsi_get_hw_state()
1710 drm_err(&dev_priv->drm, "Invalid PIPE input\n"); in gen11_dsi_get_hw_state()
1718 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in gen11_dsi_get_hw_state()
1725 if (crtc_state->dsc.compression_enable) { in gen11_dsi_initial_fastset_check()
1726 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n"); in gen11_dsi_initial_fastset_check()
1727 crtc_state->uapi.mode_changed = true; in gen11_dsi_initial_fastset_check()
1786 if (msg->flags & MIPI_DSI_MSG_USE_LPM) in gen11_dsi_host_transfer()
1790 if (mipi_dsi_packet_format_is_long(msg->type)) { in gen11_dsi_host_transfer()
1824 struct drm_device *dev = intel_dsi->base.base.dev; in icl_dphy_param_init()
1826 struct intel_connector *connector = intel_dsi->attached_connector; in icl_dphy_param_init()
1827 struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; in icl_dphy_param_init()
1836 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in icl_dphy_param_init()
1837 ths_prepare_ns = max(mipi_config->ths_prepare, in icl_dphy_param_init()
1838 mipi_config->tclk_prepare); in icl_dphy_param_init()
1849 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n", in icl_dphy_param_init()
1855 clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero - in icl_dphy_param_init()
1858 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1866 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n", in icl_dphy_param_init()
1872 tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns); in icl_dphy_param_init()
1874 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1880 tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns); in icl_dphy_param_init()
1882 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1889 hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero - in icl_dphy_param_init()
1892 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n", in icl_dphy_param_init()
1898 exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns); in icl_dphy_param_init()
1900 drm_dbg_kms(&dev_priv->drm, in icl_dphy_param_init()
1907 intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE | in icl_dphy_param_init()
1919 intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE | in icl_dphy_param_init()
1936 intel_attach_scaling_mode_property(&connector->base); in icl_dsi_add_properties()
1938 drm_connector_set_panel_orientation_with_quirk(&connector->base, in icl_dsi_add_properties()
1940 fixed_mode->hdisplay, in icl_dsi_add_properties()
1941 fixed_mode->vdisplay); in icl_dsi_add_properties()
1967 encoder = &intel_dsi->base; in icl_dsi_init()
1968 intel_dsi->attached_connector = intel_connector; in icl_dsi_init()
1969 connector = &intel_connector->base; in icl_dsi_init()
1971 encoder->devdata = devdata; in icl_dsi_init()
1974 drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs, in icl_dsi_init()
1977 encoder->pre_pll_enable = gen11_dsi_pre_pll_enable; in icl_dsi_init()
1978 encoder->pre_enable = gen11_dsi_pre_enable; in icl_dsi_init()
1979 encoder->enable = gen11_dsi_enable; in icl_dsi_init()
1980 encoder->disable = gen11_dsi_disable; in icl_dsi_init()
1981 encoder->post_disable = gen11_dsi_post_disable; in icl_dsi_init()
1982 encoder->port = port; in icl_dsi_init()
1983 encoder->get_config = gen11_dsi_get_config; in icl_dsi_init()
1984 encoder->sync_state = gen11_dsi_sync_state; in icl_dsi_init()
1985 encoder->update_pipe = intel_backlight_update; in icl_dsi_init()
1986 encoder->compute_config = gen11_dsi_compute_config; in icl_dsi_init()
1987 encoder->get_hw_state = gen11_dsi_get_hw_state; in icl_dsi_init()
1988 encoder->initial_fastset_check = gen11_dsi_initial_fastset_check; in icl_dsi_init()
1989 encoder->type = INTEL_OUTPUT_DSI; in icl_dsi_init()
1990 encoder->cloneable = 0; in icl_dsi_init()
1991 encoder->pipe_mask = ~0; in icl_dsi_init()
1992 encoder->power_domain = POWER_DOMAIN_PORT_DSI; in icl_dsi_init()
1993 encoder->get_power_domains = gen11_dsi_get_power_domains; in icl_dsi_init()
1994 encoder->disable_clock = gen11_dsi_gate_clocks; in icl_dsi_init()
1995 encoder->is_clock_enabled = gen11_dsi_is_clock_enabled; in icl_dsi_init()
1996 encoder->shutdown = intel_dsi_shutdown; in icl_dsi_init()
1999 drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs, in icl_dsi_init()
2002 connector->display_info.subpixel_order = SubPixelHorizontalRGB; in icl_dsi_init()
2003 intel_connector->get_hw_state = intel_connector_get_hw_state; in icl_dsi_init()
2008 intel_dsi->panel_power_off_time = ktime_get_boottime(); in icl_dsi_init()
2010 intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL); in icl_dsi_init()
2012 mutex_lock(&dev_priv->drm.mode_config.mutex); in icl_dsi_init()
2014 mutex_unlock(&dev_priv->drm.mode_config.mutex); in icl_dsi_init()
2017 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n"); in icl_dsi_init()
2025 if (intel_connector->panel.vbt.dsi.config->dual_link) in icl_dsi_init()
2026 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
2028 intel_dsi->ports = BIT(port); in icl_dsi_init()
2030 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports)) in icl_dsi_init()
2031 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports; in icl_dsi_init()
2033 if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports)) in icl_dsi_init()
2034 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports; in icl_dsi_init()
2036 for_each_dsi_port(port, intel_dsi->ports) { in icl_dsi_init()
2043 intel_dsi->dsi_hosts[port] = host; in icl_dsi_init()
2047 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in icl_dsi_init()
2058 drm_encoder_cleanup(&encoder->base); in icl_dsi_init()