Lines Matching refs:crtc
264 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_get_fifo_size() local
265 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_get_fifo_size()
267 enum pipe pipe = crtc->pipe; in vlv_get_fifo_size()
596 static bool intel_crtc_active(struct intel_crtc *crtc) in intel_crtc_active() argument
611 return crtc && crtc->active && crtc->base.primary->state->fb && in intel_crtc_active()
612 crtc->config->hw.adjusted_mode.crtc_clock; in intel_crtc_active()
617 struct intel_crtc *crtc, *enabled = NULL; in single_enabled_crtc() local
619 for_each_intel_crtc(&dev_priv->drm, crtc) { in single_enabled_crtc()
620 if (intel_crtc_active(crtc)) { in single_enabled_crtc()
623 enabled = crtc; in single_enabled_crtc()
632 struct intel_crtc *crtc; in pnv_update_wm() local
648 crtc = single_enabled_crtc(dev_priv); in pnv_update_wm()
649 if (crtc) { in pnv_update_wm()
651 crtc->base.primary->state->fb; in pnv_update_wm()
652 int pixel_rate = crtc->config->pixel_rate; in pnv_update_wm()
932 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in g4x_raw_plane_wm_set()
948 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in g4x_raw_fbc_wm_set()
972 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in g4x_raw_plane_wm_compute()
1052 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in g4x_raw_crtc_wm_is_valid()
1063 static void g4x_invalidate_wms(struct intel_crtc *crtc, in g4x_invalidate_wms() argument
1069 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_invalidate_wms()
1107 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _g4x_compute_pipe_wm() local
1119 for_each_plane_id_on_crtc(crtc, plane_id) in _g4x_compute_pipe_wm()
1151 g4x_invalidate_wms(crtc, wm_state, level); in _g4x_compute_pipe_wm()
1166 struct intel_crtc *crtc) in g4x_compute_pipe_wm() argument
1169 intel_atomic_get_new_crtc_state(state, crtc); in g4x_compute_pipe_wm()
1179 if (new_plane_state->hw.crtc != &crtc->base && in g4x_compute_pipe_wm()
1180 old_plane_state->hw.crtc != &crtc->base) in g4x_compute_pipe_wm()
1194 struct intel_crtc *crtc) in g4x_compute_intermediate_wm() argument
1196 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in g4x_compute_intermediate_wm()
1198 intel_atomic_get_new_crtc_state(state, crtc); in g4x_compute_intermediate_wm()
1200 intel_atomic_get_old_crtc_state(state, crtc); in g4x_compute_intermediate_wm()
1221 for_each_plane_id_on_crtc(crtc, plane_id) { in g4x_compute_intermediate_wm()
1278 struct intel_crtc *crtc; in g4x_merge_wm() local
1285 for_each_intel_crtc(&dev_priv->drm, crtc) { in g4x_merge_wm()
1286 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1288 if (!crtc->active) in g4x_merge_wm()
1307 for_each_intel_crtc(&dev_priv->drm, crtc) { in g4x_merge_wm()
1308 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1309 enum pipe pipe = crtc->pipe; in g4x_merge_wm()
1312 if (crtc->active && wm->cxsr) in g4x_merge_wm()
1314 if (crtc->active && wm->hpll_en) in g4x_merge_wm()
1341 struct intel_crtc *crtc) in g4x_initial_watermarks() argument
1343 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in g4x_initial_watermarks()
1345 intel_atomic_get_new_crtc_state(state, crtc); in g4x_initial_watermarks()
1348 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; in g4x_initial_watermarks()
1354 struct intel_crtc *crtc) in g4x_optimize_watermarks() argument
1356 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in g4x_optimize_watermarks()
1358 intel_atomic_get_new_crtc_state(state, crtc); in g4x_optimize_watermarks()
1364 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_optimize_watermarks()
1445 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_compute_fifo() local
1446 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_compute_fifo()
1480 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_fifo()
1501 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_fifo()
1527 static void vlv_invalidate_wms(struct intel_crtc *crtc, in vlv_invalidate_wms() argument
1530 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_invalidate_wms()
1535 for_each_plane_id_on_crtc(crtc, plane_id) in vlv_invalidate_wms()
1558 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in vlv_raw_plane_wm_set()
1575 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in vlv_raw_plane_wm_compute()
1633 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in _vlv_compute_pipe_wm() local
1634 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in _vlv_compute_pipe_wm()
1650 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; in _vlv_compute_pipe_wm()
1659 for_each_plane_id_on_crtc(crtc, plane_id) { in _vlv_compute_pipe_wm()
1683 vlv_invalidate_wms(crtc, wm_state, level); in _vlv_compute_pipe_wm()
1689 struct intel_crtc *crtc) in vlv_compute_pipe_wm() argument
1692 intel_atomic_get_new_crtc_state(state, crtc); in vlv_compute_pipe_wm()
1702 if (new_plane_state->hw.crtc != &crtc->base && in vlv_compute_pipe_wm()
1703 old_plane_state->hw.crtc != &crtc->base) in vlv_compute_pipe_wm()
1728 intel_atomic_get_old_crtc_state(state, crtc); in vlv_compute_pipe_wm()
1752 struct intel_crtc *crtc) in vlv_atomic_update_fifo() argument
1754 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_atomic_update_fifo()
1757 intel_atomic_get_new_crtc_state(state, crtc); in vlv_atomic_update_fifo()
1773 trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size); in vlv_atomic_update_fifo()
1786 switch (crtc->pipe) { in vlv_atomic_update_fifo()
1850 struct intel_crtc *crtc) in vlv_compute_intermediate_wm() argument
1853 intel_atomic_get_new_crtc_state(state, crtc); in vlv_compute_intermediate_wm()
1855 intel_atomic_get_old_crtc_state(state, crtc); in vlv_compute_intermediate_wm()
1876 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_intermediate_wm()
1888 vlv_invalidate_wms(crtc, intermediate, level); in vlv_compute_intermediate_wm()
1904 struct intel_crtc *crtc; in vlv_merge_wm() local
1910 for_each_intel_crtc(&dev_priv->drm, crtc) { in vlv_merge_wm()
1911 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
1913 if (!crtc->active) in vlv_merge_wm()
1929 for_each_intel_crtc(&dev_priv->drm, crtc) { in vlv_merge_wm()
1930 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
1931 enum pipe pipe = crtc->pipe; in vlv_merge_wm()
1934 if (crtc->active && wm->cxsr) in vlv_merge_wm()
1978 struct intel_crtc *crtc) in vlv_initial_watermarks() argument
1980 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_initial_watermarks()
1982 intel_atomic_get_new_crtc_state(state, crtc); in vlv_initial_watermarks()
1985 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; in vlv_initial_watermarks()
1991 struct intel_crtc *crtc) in vlv_optimize_watermarks() argument
1993 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in vlv_optimize_watermarks()
1995 intel_atomic_get_new_crtc_state(state, crtc); in vlv_optimize_watermarks()
2001 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_optimize_watermarks()
2008 struct intel_crtc *crtc; in i965_update_wm() local
2014 crtc = single_enabled_crtc(dev_priv); in i965_update_wm()
2015 if (crtc) { in i965_update_wm()
2019 &crtc->config->hw.pipe_mode; in i965_update_wm()
2021 crtc->base.primary->state->fb; in i965_update_wm()
2022 int pixel_rate = crtc->config->pixel_rate; in i965_update_wm()
2024 int width = drm_rect_width(&crtc->base.primary->state->src) >> 16; in i965_update_wm()
2040 crtc->base.cursor->state->crtc_w, 4, in i965_update_wm()
2103 struct intel_crtc *crtc; in i9xx_update_wm() local
2116 crtc = intel_crtc_for_plane(dev_priv, PLANE_A); in i9xx_update_wm()
2117 if (intel_crtc_active(crtc)) { in i9xx_update_wm()
2119 crtc->base.primary->state->fb; in i9xx_update_wm()
2127 planea_wm = intel_calculate_wm(crtc->config->pixel_rate, in i9xx_update_wm()
2143 crtc = intel_crtc_for_plane(dev_priv, PLANE_B); in i9xx_update_wm()
2144 if (intel_crtc_active(crtc)) { in i9xx_update_wm()
2146 crtc->base.primary->state->fb; in i9xx_update_wm()
2154 planeb_wm = intel_calculate_wm(crtc->config->pixel_rate, in i9xx_update_wm()
2166 crtc = single_enabled_crtc(dev_priv); in i9xx_update_wm()
2167 if (IS_I915GM(dev_priv) && crtc) { in i9xx_update_wm()
2170 obj = intel_fb_obj(crtc->base.primary->state->fb); in i9xx_update_wm()
2174 crtc = NULL; in i9xx_update_wm()
2186 if (HAS_FW_BLC(dev_priv) && crtc) { in i9xx_update_wm()
2190 &crtc->config->hw.pipe_mode; in i9xx_update_wm()
2192 crtc->base.primary->state->fb; in i9xx_update_wm()
2193 int pixel_rate = crtc->config->pixel_rate; in i9xx_update_wm()
2195 int width = drm_rect_width(&crtc->base.primary->state->src) >> 16; in i9xx_update_wm()
2234 if (crtc) in i9xx_update_wm()
2240 struct intel_crtc *crtc; in i845_update_wm() local
2244 crtc = single_enabled_crtc(dev_priv); in i845_update_wm()
2245 if (crtc == NULL) in i845_update_wm()
2248 planea_wm = intel_calculate_wm(crtc->config->pixel_rate, in i845_update_wm()
2576 const struct intel_crtc *crtc, in ilk_compute_wm_level() argument
2789 struct intel_crtc *crtc) in ilk_compute_pipe_wm() argument
2793 intel_atomic_get_new_crtc_state(state, crtc); in ilk_compute_pipe_wm()
2829 ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state, in ilk_compute_pipe_wm()
2840 ilk_compute_wm_level(dev_priv, crtc, level, crtc_state, in ilk_compute_pipe_wm()
2863 struct intel_crtc *crtc) in ilk_compute_intermediate_wm() argument
2865 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_compute_intermediate_wm()
2867 intel_atomic_get_new_crtc_state(state, crtc); in ilk_compute_intermediate_wm()
2869 intel_atomic_get_old_crtc_state(state, crtc); in ilk_compute_intermediate_wm()
2926 const struct intel_crtc *crtc; in ilk_merge_wm_level() local
2930 for_each_intel_crtc(&dev_priv->drm, crtc) { in ilk_merge_wm_level()
2931 const struct intel_pipe_wm *active = &crtc->wm.active.ilk; in ilk_merge_wm_level()
3026 struct intel_crtc *crtc; in ilk_compute_wm_results() local
3070 for_each_intel_crtc(&dev_priv->drm, crtc) { in ilk_compute_wm_results()
3071 enum pipe pipe = crtc->pipe; in ilk_compute_wm_results()
3072 const struct intel_pipe_wm *pipe_wm = &crtc->wm.active.ilk; in ilk_compute_wm_results()
3265 struct intel_crtc *crtc; in ilk_compute_wm_config() local
3268 for_each_intel_crtc(&dev_priv->drm, crtc) { in ilk_compute_wm_config()
3269 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; in ilk_compute_wm_config()
3313 struct intel_crtc *crtc) in ilk_initial_watermarks() argument
3315 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_initial_watermarks()
3317 intel_atomic_get_new_crtc_state(state, crtc); in ilk_initial_watermarks()
3320 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate; in ilk_initial_watermarks()
3326 struct intel_crtc *crtc) in ilk_optimize_watermarks() argument
3328 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in ilk_optimize_watermarks()
3330 intel_atomic_get_new_crtc_state(state, crtc); in ilk_optimize_watermarks()
3336 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal; in ilk_optimize_watermarks()
3341 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc) in ilk_pipe_wm_get_hw_state() argument
3343 struct drm_device *dev = crtc->base.dev; in ilk_pipe_wm_get_hw_state()
3346 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); in ilk_pipe_wm_get_hw_state()
3348 enum pipe pipe = crtc->pipe; in ilk_pipe_wm_get_hw_state()
3354 active->pipe_enabled = crtc->active; in ilk_pipe_wm_get_hw_state()
3381 crtc->wm.active.ilk = *active; in ilk_pipe_wm_get_hw_state()
3387 struct intel_crtc *crtc; in ilk_sanitize_watermarks_add_affected() local
3389 for_each_intel_crtc(state->dev, crtc) { in ilk_sanitize_watermarks_add_affected()
3392 crtc_state = intel_atomic_get_crtc_state(state, crtc); in ilk_sanitize_watermarks_add_affected()
3430 struct intel_crtc *crtc; in ilk_wm_sanitize() local
3472 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) { in ilk_wm_sanitize()
3474 intel_optimize_watermarks(intel_state, crtc); in ilk_wm_sanitize()
3476 to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; in ilk_wm_sanitize()
3616 struct intel_crtc *crtc; in g4x_wm_get_hw_state() local
3622 for_each_intel_crtc(&dev_priv->drm, crtc) { in g4x_wm_get_hw_state()
3624 to_intel_crtc_state(crtc->base.state); in g4x_wm_get_hw_state()
3625 struct g4x_wm_state *active = &crtc->wm.active.g4x; in g4x_wm_get_hw_state()
3627 enum pipe pipe = crtc->pipe; in g4x_wm_get_hw_state()
3638 for_each_plane_id_on_crtc(crtc, plane_id) { in g4x_wm_get_hw_state()
3652 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_wm_get_hw_state()
3677 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_wm_get_hw_state()
3682 g4x_invalidate_wms(crtc, active, level); in g4x_wm_get_hw_state()
3709 struct intel_crtc *crtc; in g4x_wm_sanitize() local
3714 struct intel_crtc *crtc = in g4x_wm_sanitize() local
3717 to_intel_crtc_state(crtc->base.state); in g4x_wm_sanitize()
3737 for_each_intel_crtc(&dev_priv->drm, crtc) { in g4x_wm_sanitize()
3739 to_intel_crtc_state(crtc->base.state); in g4x_wm_sanitize()
3747 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
3764 struct intel_crtc *crtc; in vlv_wm_get_hw_state() local
3807 for_each_intel_crtc(&dev_priv->drm, crtc) { in vlv_wm_get_hw_state()
3809 to_intel_crtc_state(crtc->base.state); in vlv_wm_get_hw_state()
3810 struct vlv_wm_state *active = &crtc->wm.active.vlv; in vlv_wm_get_hw_state()
3813 enum pipe pipe = crtc->pipe; in vlv_wm_get_hw_state()
3829 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_wm_get_hw_state()
3839 for_each_plane_id_on_crtc(crtc, plane_id) in vlv_wm_get_hw_state()
3842 vlv_invalidate_wms(crtc, active, level); in vlv_wm_get_hw_state()
3864 struct intel_crtc *crtc; in vlv_wm_sanitize() local
3869 struct intel_crtc *crtc = in vlv_wm_sanitize() local
3872 to_intel_crtc_state(crtc->base.state); in vlv_wm_sanitize()
3889 for_each_intel_crtc(&dev_priv->drm, crtc) { in vlv_wm_sanitize()
3891 to_intel_crtc_state(crtc->base.state); in vlv_wm_sanitize()
3899 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
3932 struct intel_crtc *crtc; in ilk_wm_get_hw_state() local
3936 for_each_intel_crtc(&dev_priv->drm, crtc) in ilk_wm_get_hw_state()
3937 ilk_pipe_wm_get_hw_state(crtc); in ilk_wm_get_hw_state()