120 	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;  in intel_dp_prepare()
170 	bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;  in assert_dp_port()
309 	ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,  in intel_dp_get_hw_state()
346 	tmp = intel_de_read(dev_priv, intel_dp->output_reg);  in intel_dp_get_config()
418 			(intel_de_read(dev_priv, intel_dp->output_reg) &  in intel_dp_link_down()
432 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
433 	intel_de_posting_read(dev_priv, intel_dp->output_reg);  in intel_dp_link_down()
436 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
437 	intel_de_posting_read(dev_priv, intel_dp->output_reg);  in intel_dp_link_down()
456 		intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
457 		intel_de_posting_read(dev_priv, intel_dp->output_reg);  in intel_dp_link_down()
460 		intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
461 		intel_de_posting_read(dev_priv, intel_dp->output_reg);  in intel_dp_link_down()
585 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in cpt_set_link_train()
586 	intel_de_posting_read(dev_priv, intel_dp->output_reg);  in cpt_set_link_train()
613 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in g4x_set_link_train()
614 	intel_de_posting_read(dev_priv, intel_dp->output_reg);  in g4x_set_link_train()
637 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in intel_dp_enable_port()
638 	intel_de_posting_read(dev_priv, intel_dp->output_reg);  in intel_dp_enable_port()
648 	u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);  in intel_enable_dp()
1013 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in g4x_set_signal_levels()
1014 	intel_de_posting_read(dev_priv, intel_dp->output_reg);  in g4x_set_signal_levels()
1061 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in snb_cpu_edp_set_signal_levels()
1062 	intel_de_posting_read(dev_priv, intel_dp->output_reg);  in snb_cpu_edp_set_signal_levels()
1113 	intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);  in ivb_cpu_edp_set_signal_levels()
1114 	intel_de_posting_read(dev_priv, intel_dp->output_reg);  in ivb_cpu_edp_set_signal_levels()
1228 	if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,  in vlv_active_pipe()
1240 	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);  in intel_dp_encoder_reset()
1260 		 i915_reg_t output_reg, enum port port)  in g4x_dp_init()  argument
1355 	dig_port->dp.output_reg = output_reg;  in g4x_dp_init()