126 	writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) |  in hibmc_plane_atomic_update()
127 	       HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_OFFS, line_l),  in hibmc_plane_atomic_update()
133 	reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT,  in hibmc_plane_atomic_update()
167 	reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms);  in hibmc_crtc_dpms()
243 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_BYPASS, 0);  in format_pll_reg()
244 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POWER, 1);  in format_pll_reg()
245 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_INPUT, 0);  in format_pll_reg()
246 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_POD, pll.POD);  in format_pll_reg()
247 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_OD, pll.OD);  in format_pll_reg()
248 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_N, pll.N);  in format_pll_reg()
249 	pllreg |= HIBMC_FIELD(HIBMC_PLL_CTRL_M, pll.M);  in format_pll_reg()
332 	writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_TOP, 0) |  in display_ctrl_adjust()
333 	       HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_TL_LEFT, 0),  in display_ctrl_adjust()
336 	writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) |  in display_ctrl_adjust()
337 	       HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1),  in display_ctrl_adjust()
370 	writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) |  in hibmc_crtc_mode_set_nofb()
371 	       HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1),  in hibmc_crtc_mode_set_nofb()
374 	writel(HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_WIDTH, width) |  in hibmc_crtc_mode_set_nofb()
375 	       HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1),  in hibmc_crtc_mode_set_nofb()
378 	writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) |  in hibmc_crtc_mode_set_nofb()
379 	       HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1),  in hibmc_crtc_mode_set_nofb()
382 	writel(HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_HEIGHT, height) |  in hibmc_crtc_mode_set_nofb()
383 	       HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1),  in hibmc_crtc_mode_set_nofb()
386 	val = HIBMC_FIELD(HIBMC_CRT_DISP_CTL_VSYNC_PHASE, 0);  in hibmc_crtc_mode_set_nofb()
387 	val |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_HSYNC_PHASE, 0);  in hibmc_crtc_mode_set_nofb()
468 	reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1);  in hibmc_crtc_load_lut()