Lines Matching refs:GMBUS_REG_WRITE
56 #define GMBUS_REG_WRITE(reg, val) iowrite32((val), dev_priv->gmbus_reg + (reg)) macro
79 GMBUS_REG_WRITE(GMBUS0, 0); in gma_intel_i2c_reset()
121 GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK); in get_clock()
122 GMBUS_REG_WRITE(gpio->reg, reserved); in get_clock()
131 GMBUS_REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK); in get_data()
132 GMBUS_REG_WRITE(gpio->reg, reserved); in get_data()
149 GMBUS_REG_WRITE(gpio->reg, reserved | clock_bits); in set_clock()
166 GMBUS_REG_WRITE(gpio->reg, reserved | data_bits); in set_data()
262 GMBUS_REG_WRITE(GMBUS0 + reg_offset, bus->reg0); in gmbus_xfer()
269 GMBUS_REG_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
299 GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer()
300 GMBUS_REG_WRITE(GMBUS1 + reg_offset, in gmbus_xfer()
320 GMBUS_REG_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer()
338 GMBUS_REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT); in gmbus_xfer()
339 GMBUS_REG_WRITE(GMBUS1 + reg_offset, 0); in gmbus_xfer()
345 GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0); in gmbus_xfer()
351 GMBUS_REG_WRITE(GMBUS0 + reg_offset, 0); in gmbus_xfer()