Lines Matching refs:lane_value
223 u32 lane_reg, lane_value; in cdv_dpll_set_clock_cdv() local
337 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
338 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
339 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
340 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()
343 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
344 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
345 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
346 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()
349 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
350 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
351 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
352 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()
355 cdv_sb_read(dev, lane_reg, &lane_value); in cdv_dpll_set_clock_cdv()
356 lane_value &= ~(LANE_PLL_MASK); in cdv_dpll_set_clock_cdv()
357 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()
358 cdv_sb_write(dev, lane_reg, lane_value); in cdv_dpll_set_clock_cdv()