39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)  in etnaviv_gpu_get_param()
186 		u32 specs[4];  in etnaviv_hw_specs()
334 	u32 chipIdentity;  in etnaviv_hw_identify()
344 		u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);  in etnaviv_hw_identify()
372 			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);  in etnaviv_hw_identify()
473 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)  in etnaviv_gpu_load_clock()
490 		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_gpu_update_clock()
508 	u32 control, idle;  in etnaviv_hw_reset()
598 	u32 pmc, ppc;  in etnaviv_gpu_enable_mlcg()
650 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)  in etnaviv_gpu_start_fe()
668 	u32 address;  in etnaviv_gpu_start_fe_idleloop()
691 	u32 pulse_eater = 0x01590880;  in etnaviv_gpu_setup_pulse_eater()
724 		u32 mc_memory_debug;  in etnaviv_gpu_hw_init()
749 		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);  in etnaviv_gpu_hw_init()
758 		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);  in etnaviv_gpu_hw_init()
891 	u32 address[2];
892 	u32 state[2];
897 	u32 i;  in verify_dma()
917 	u32 dma_lo, dma_hi, axi, idle;  in etnaviv_gpu_debugfs()
1039 		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);  in etnaviv_gpu_debugfs()
1040 		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);  in etnaviv_gpu_debugfs()
1041 		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);  in etnaviv_gpu_debugfs()
1144 static inline bool fence_after(u32 a, u32 b)  in fence_after()
1223 	u32 id, struct drm_etnaviv_timespec *timeout)  in etnaviv_gpu_wait_fence_interruptible()
1309 	u32 val;  in sync_point_perfmon_sample_pre()
1329 	u32 val;  in sync_point_perfmon_sample_post()
1423 	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in sync_point_worker()
1487 	u32 status_reg, status;  in dump_mmu_fault()
1500 		u32 address_reg;  in dump_mmu_fault()
1501 		u32 mmu_status;  in dump_mmu_fault()
1526 	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);  in irq_handler()
1636 		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_gpu_wait_idle()
1917 	u32 idle, mask;  in etnaviv_gpu_rpm_suspend()