802 			       const u8 port_cap[4], u8 type)  in drm_dp_downstream_is_type()
806 		(port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;  in drm_dp_downstream_is_type()
819 			       const u8 port_cap[4],  in drm_dp_downstream_is_tmds()
831 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_is_tmds()
1048 				   const u8 port_cap[4])  in drm_dp_downstream_max_dotclock()
1056 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_max_dotclock()
1060 		return port_cap[1] * 8000;  in drm_dp_downstream_max_dotclock()
1077 				     const u8 port_cap[4],  in drm_dp_downstream_max_tmds_clock()
1092 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_max_tmds_clock()
1120 		return port_cap[1] * 2500;  in drm_dp_downstream_max_tmds_clock()
1125 		return port_cap[1] * 2500;  in drm_dp_downstream_max_tmds_clock()
1142 				     const u8 port_cap[4],  in drm_dp_downstream_min_tmds_clock()
1157 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_min_tmds_clock()
1185 			      const u8 port_cap[4],  in drm_dp_downstream_max_bpc()
1200 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_max_bpc()
1213 		switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {  in drm_dp_downstream_max_bpc()
1241 				       const u8 port_cap[4])  in drm_dp_downstream_420_passthrough()
1249 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_420_passthrough()
1256 		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;  in drm_dp_downstream_420_passthrough()
1272 					     const u8 port_cap[4])  in drm_dp_downstream_444_to_420_conversion()
1280 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_444_to_420_conversion()
1285 		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;  in drm_dp_downstream_444_to_420_conversion()
1303 					       const u8 port_cap[4],  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1312 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1317 		return port_cap[3] & color_spc;  in drm_dp_downstream_rgb_to_ycbcr_conversion()
1337 		       const u8 port_cap[4])  in drm_dp_downstream_mode()
1348 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {  in drm_dp_downstream_mode()
1350 		switch (port_cap[0] & DP_DS_NON_EDID_MASK) {  in drm_dp_downstream_mode()
1403 			     const u8 port_cap[4],  in drm_dp_downstream_debug()
1414 	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;  in drm_dp_downstream_debug()
1463 		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);  in drm_dp_downstream_debug()
1467 		clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1471 		clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1475 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);  in drm_dp_downstream_debug()
1490 			 const u8 port_cap[4])  in drm_dp_subconnector_type()
1514 	type = port_cap[0] & DP_DS_PORT_TYPE_MASK;  in drm_dp_subconnector_type()
1547 				      const u8 port_cap[4])  in drm_dp_set_subconnector_property()
1552 		subconnector = drm_dp_subconnector_type(dpcd, port_cap);  in drm_dp_set_subconnector_property()
2928 			       const u8 port_cap[4])  in drm_dp_get_pcon_max_frl_bw()
2933 	buf = port_cap[2];  in drm_dp_get_pcon_max_frl_bw()