Lines Matching +full:phy +full:- +full:dsi +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
50 /* DSI PPI Layer Registers */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
58 #define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
72 #define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */
73 #define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */
74 #define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */
75 #define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */
76 #define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */
77 #define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */
78 #define D0S_PREP 0x01A4 /* Digital Counter inside of PHY IO */
79 #define D1S_PREP 0x01A8 /* Digital Counter inside of PHY IO */
80 #define D2S_PREP 0x01AC /* Digital Counter inside of PHY IO */
81 #define D3S_PREP 0x01B0 /* Digital Counter inside of PHY IO */
82 #define CLS_ZERO 0x01C0 /* Digital Counter inside of PHY IO */
83 #define D0S_ZERO 0x01C4 /* Digital Counter inside of PHY IO */
84 #define D1S_ZERO 0x01C8 /* Digital Counter inside of PHY IO */
85 #define D2S_ZERO 0x01CC /* Digital Counter inside of PHY IO */
86 #define D3S_ZERO 0x01D0 /* Digital Counter inside of PHY IO */
92 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
105 #define DSIERRCNT 0x0300 /* DSI Error Count */
161 #define LVPHY0 0x04A0 /* LVDS PHY 0 */
162 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
167 #define LVPHY1 0x04A4 /* LVDS PHY 1 */
171 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
172 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
175 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
265 struct mipi_dsi_device *dsi; member
272 u8 lvds_link; /* single-link or dual-link */
284 struct device *dev = &tc->dsi->dev; in tc_bridge_pre_enable()
287 ret = regulator_enable(tc->vddio); in tc_bridge_pre_enable()
292 ret = regulator_enable(tc->vdd); in tc_bridge_pre_enable()
297 gpiod_set_value(tc->stby_gpio, 0); in tc_bridge_pre_enable()
300 gpiod_set_value(tc->reset_gpio, 0); in tc_bridge_pre_enable()
307 struct device *dev = &tc->dsi->dev; in tc_bridge_post_disable()
310 gpiod_set_value(tc->reset_gpio, 1); in tc_bridge_post_disable()
313 gpiod_set_value(tc->stby_gpio, 1); in tc_bridge_post_disable()
316 ret = regulator_disable(tc->vdd); in tc_bridge_post_disable()
321 ret = regulator_disable(tc->vddio); in tc_bridge_post_disable()
345 dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n", in d2l_read()
359 dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n", in d2l_write()
366 struct drm_device *dev = encoder->dev; in get_connector()
369 list_for_each_entry(connector, &dev->mode_config.connector_list, head) in get_connector()
370 if (connector->encoder == encoder) in get_connector()
384 struct drm_connector *connector = get_connector(bridge->encoder); in tc_bridge_enable()
386 mode = &bridge->encoder->crtc->state->adjusted_mode; in tc_bridge_enable()
388 hback_porch = mode->htotal - mode->hsync_end; in tc_bridge_enable()
389 hsync_len = mode->hsync_end - mode->hsync_start; in tc_bridge_enable()
390 vback_porch = mode->vtotal - mode->vsync_end; in tc_bridge_enable()
391 vsync_len = mode->vsync_end - mode->vsync_start; in tc_bridge_enable()
396 hfront_porch = mode->hsync_start - mode->hdisplay; in tc_bridge_enable()
397 hactive = mode->hdisplay; in tc_bridge_enable()
398 vfront_porch = mode->vsync_start - mode->vdisplay; in tc_bridge_enable()
399 vactive = mode->vdisplay; in tc_bridge_enable()
404 d2l_read(tc->i2c, IDREG, &val); in tc_bridge_enable()
406 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n", in tc_bridge_enable()
409 d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM | in tc_bridge_enable()
413 d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE); in tc_bridge_enable()
414 d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD); in tc_bridge_enable()
415 d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
416 d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
417 d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
418 d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3); in tc_bridge_enable()
420 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT; in tc_bridge_enable()
421 d2l_write(tc->i2c, PPI_LANEENABLE, val); in tc_bridge_enable()
422 d2l_write(tc->i2c, DSI_LANEENABLE, val); in tc_bridge_enable()
424 d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION); in tc_bridge_enable()
425 d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START); in tc_bridge_enable()
427 if (tc->bpc == 8) in tc_bridge_enable()
432 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000; in tc_bridge_enable()
433 clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3); in tc_bridge_enable()
435 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes; in tc_bridge_enable()
437 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) / in tc_bridge_enable()
438 tc->num_dsi_lanes); in tc_bridge_enable()
440 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive; in tc_bridge_enable()
443 d2l_write(tc->i2c, VPCTRL, val); in tc_bridge_enable()
445 d2l_write(tc->i2c, HTIM1, htime1); in tc_bridge_enable()
446 d2l_write(tc->i2c, VTIM1, vtime1); in tc_bridge_enable()
447 d2l_write(tc->i2c, HTIM2, htime2); in tc_bridge_enable()
448 d2l_write(tc->i2c, VTIM2, vtime2); in tc_bridge_enable()
450 d2l_write(tc->i2c, VFUEN, VFUEN_EN); in tc_bridge_enable()
451 d2l_write(tc->i2c, SYSRST, SYS_RST_LCD); in tc_bridge_enable()
452 d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6)); in tc_bridge_enable()
454 dev_dbg(tc->dev, "bus_formats %04x bpc %d\n", in tc_bridge_enable()
455 connector->display_info.bus_formats[0], in tc_bridge_enable()
456 tc->bpc); in tc_bridge_enable()
457 if (connector->display_info.bus_formats[0] == in tc_bridge_enable()
459 /* VESA-24 */ in tc_bridge_enable()
460 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); in tc_bridge_enable()
461 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); in tc_bridge_enable()
462 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); in tc_bridge_enable()
463 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); in tc_bridge_enable()
464 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); in tc_bridge_enable()
465 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); in tc_bridge_enable()
466 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); in tc_bridge_enable()
468 /* JEIDA-18 and JEIDA-24 */ in tc_bridge_enable()
469 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R2, LVI_R3, LVI_R4, LVI_R5)); in tc_bridge_enable()
470 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R6, LVI_R1, LVI_R7, LVI_G2)); in tc_bridge_enable()
471 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G3, LVI_G4, LVI_G0, LVI_G1)); in tc_bridge_enable()
472 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G5, LVI_G6, LVI_G7, LVI_B2)); in tc_bridge_enable()
473 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B0, LVI_B1, LVI_B3, LVI_B4)); in tc_bridge_enable()
474 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B5, LVI_B6, LVI_B7, LVI_L0)); in tc_bridge_enable()
475 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R0)); in tc_bridge_enable()
478 d2l_write(tc->i2c, VFUEN, VFUEN_EN); in tc_bridge_enable()
481 if (tc->lvds_link == DUAL_LINK) { in tc_bridge_enable()
487 d2l_write(tc->i2c, LVCFG, val); in tc_bridge_enable()
498 * Maximum pixel clock speed 135MHz for single-link in tc_mode_valid()
499 * 270MHz for dual-link in tc_mode_valid()
501 if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) || in tc_mode_valid()
502 (mode->clock > 270000 && tc->lvds_link == DUAL_LINK)) in tc_mode_valid()
505 switch (info->bus_formats[0]) { in tc_mode_valid()
509 tc->bpc = 8; in tc_mode_valid()
513 tc->bpc = 6; in tc_mode_valid()
516 dev_warn(tc->dev, in tc_mode_valid()
518 info->bus_formats[0]); in tc_mode_valid()
530 int dsi_lanes = -1; in tc358775_parse_dt()
533 * To get the data-lanes of dsi, we need to access the dsi0_out of port1 in tc358775_parse_dt()
536 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, in tc358775_parse_dt()
537 TC358775_DSI_IN, -1); in tc358775_parse_dt()
544 dsi_lanes = drm_of_get_data_lanes_count_ep(parent, 1, -1, 1, 4); in tc358775_parse_dt()
552 tc->num_dsi_lanes = dsi_lanes; in tc358775_parse_dt()
554 tc->host_node = of_graph_get_remote_node(np, 0, 0); in tc358775_parse_dt()
555 if (!tc->host_node) in tc358775_parse_dt()
556 return -ENODEV; in tc358775_parse_dt()
558 of_node_put(tc->host_node); in tc358775_parse_dt()
560 tc->lvds_link = SINGLE_LINK; in tc358775_parse_dt()
561 endpoint = of_graph_get_endpoint_by_regs(tc->dev->of_node, in tc358775_parse_dt()
562 TC358775_LVDS_OUT1, -1); in tc358775_parse_dt()
569 tc->lvds_link = DUAL_LINK; in tc358775_parse_dt()
574 dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes); in tc358775_parse_dt()
575 dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link); in tc358775_parse_dt()
585 /* Attach the panel-bridge to the dsi bridge */ in tc_bridge_attach()
586 return drm_bridge_attach(bridge->encoder, tc->panel_bridge, in tc_bridge_attach()
587 &tc->bridge, flags); in tc_bridge_attach()
600 struct device *dev = &tc->i2c->dev; in tc_attach_host()
602 struct mipi_dsi_device *dsi; in tc_attach_host() local
609 host = of_find_mipi_dsi_host_by_node(tc->host_node); in tc_attach_host()
611 return dev_err_probe(dev, -EPROBE_DEFER, "failed to find dsi host\n"); in tc_attach_host()
613 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); in tc_attach_host()
614 if (IS_ERR(dsi)) { in tc_attach_host()
615 dev_err(dev, "failed to create dsi device\n"); in tc_attach_host()
616 return PTR_ERR(dsi); in tc_attach_host()
619 tc->dsi = dsi; in tc_attach_host()
621 dsi->lanes = tc->num_dsi_lanes; in tc_attach_host()
622 dsi->format = MIPI_DSI_FMT_RGB888; in tc_attach_host()
623 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; in tc_attach_host()
625 ret = devm_mipi_dsi_attach(dev, dsi); in tc_attach_host()
627 dev_err(dev, "failed to attach dsi to host\n"); in tc_attach_host()
636 struct device *dev = &client->dev; in tc_probe()
642 return -ENOMEM; in tc_probe()
644 tc->dev = dev; in tc_probe()
645 tc->i2c = client; in tc_probe()
647 tc->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, in tc_probe()
649 if (IS_ERR(tc->panel_bridge)) in tc_probe()
650 return PTR_ERR(tc->panel_bridge); in tc_probe()
652 ret = tc358775_parse_dt(dev->of_node, tc); in tc_probe()
656 tc->vddio = devm_regulator_get(dev, "vddio-supply"); in tc_probe()
657 if (IS_ERR(tc->vddio)) { in tc_probe()
658 ret = PTR_ERR(tc->vddio); in tc_probe()
659 dev_err(dev, "vddio-supply not found\n"); in tc_probe()
663 tc->vdd = devm_regulator_get(dev, "vdd-supply"); in tc_probe()
664 if (IS_ERR(tc->vdd)) { in tc_probe()
665 ret = PTR_ERR(tc->vdd); in tc_probe()
666 dev_err(dev, "vdd-supply not found\n"); in tc_probe()
670 tc->stby_gpio = devm_gpiod_get(dev, "stby", GPIOD_OUT_HIGH); in tc_probe()
671 if (IS_ERR(tc->stby_gpio)) { in tc_probe()
672 ret = PTR_ERR(tc->stby_gpio); in tc_probe()
673 dev_err(dev, "cannot get stby-gpio %d\n", ret); in tc_probe()
677 tc->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); in tc_probe()
678 if (IS_ERR(tc->reset_gpio)) { in tc_probe()
679 ret = PTR_ERR(tc->reset_gpio); in tc_probe()
680 dev_err(dev, "cannot get reset-gpios %d\n", ret); in tc_probe()
684 tc->bridge.funcs = &tc_bridge_funcs; in tc_probe()
685 tc->bridge.of_node = dev->of_node; in tc_probe()
686 drm_bridge_add(&tc->bridge); in tc_probe()
697 drm_bridge_remove(&tc->bridge); in tc_probe()
705 drm_bridge_remove(&tc->bridge); in tc_remove()
732 MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");