161 	u32 frs;	/* PLL Freqency range for HSCK (post divider) */  member
336 	u32 frs, best_diff, best_pll, best_prd, best_fbd;  in tc358768_calc_pll()  local
340 	/* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */  in tc358768_calc_pll()
349 	frs = i - 1;  in tc358768_calc_pll()
361 		u32 divisor = (prd + 1) * (1 << frs);  in tc358768_calc_pll()
401 	priv->frs = frs;  in tc358768_calc_pll()
613 	u32 fbd, prd, frs;  in tc358768_setup_pll()  local
624 	frs = priv->frs;  in tc358768_setup_pll()
626 	dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",  in tc358768_setup_pll()
627 		clk_get_rate(priv->refclk), fbd, prd, frs);  in tc358768_setup_pll()
637 	/* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */  in tc358768_setup_pll()
639 		       (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));  in tc358768_setup_pll()
644 	/* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */  in tc358768_setup_pll()
646 		       (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));  in tc358768_setup_pll()