Lines Matching defs:v
49 #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ argument
54 #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16) argument
55 #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0) argument
57 #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16) argument
58 #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0) argument
60 #define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16) argument
61 #define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0) argument
63 #define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16) argument
64 #define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0) argument
112 #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */ argument
113 #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14) argument
114 #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */ argument
115 #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */ argument
210 u32 v = 0; in tc358764_init() local