284 #define mhl_tx_writeb(sii9234, offset, value) \  macro
418 	mhl_tx_writeb(ctx, 0x08, 0x35);  in sii9234_power_init()
434 	mhl_tx_writeb(ctx, MHL_TX_TMDS_CCTRL, 0x34);  in sii9234_hdmi_init()
444 	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0xD0);  in sii9234_mhl_tx_ctl_int()
445 	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL2_REG, 0xFC);  in sii9234_mhl_tx_ctl_int()
446 	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL4_REG, 0xEB);  in sii9234_mhl_tx_ctl_int()
447 	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL7_REG, 0x0C);  in sii9234_mhl_tx_ctl_int()
472 	mhl_tx_writeb(ctx, 0x2B, 0x01);  in sii9234_reset()
476 	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL2_REG, (1 << 7) /* Reserved */  in sii9234_reset()
483 	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77);  in sii9234_reset()
485 	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL6_REG, 0xA0);  in sii9234_reset()
487 	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL6_REG, BLOCK_RGND_INT |  in sii9234_reset()
490 	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL8_REG, 0);  in sii9234_reset()
515 	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL1_REG, 0x27);  in sii9234_reset()
525 	mhl_tx_writeb(ctx, 0x05, 0x04);  in sii9234_reset()
527 	mhl_tx_writeb(ctx, 0x0D, 0x1C);  in sii9234_reset()
528 	mhl_tx_writeb(ctx, MHL_TX_INTR4_ENABLE_REG,  in sii9234_reset()
531 	mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG, 0x60);  in sii9234_reset()
659 	mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77);  in sii9234_rgnd_ready_irq()
673 	mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0x10);  in sii9234_mhl_established()
679 	mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG,  in sii9234_mhl_established()
790 	mhl_tx_writeb(ctx, MHL_TX_INTR1_REG, intr1);  in sii9234_irq_thread()
791 	mhl_tx_writeb(ctx, MHL_TX_INTR4_REG, intr4);  in sii9234_irq_thread()