427 	u8 dpcd[DP_RECEIVER_CAP_SIZE];  member
626 static int it6505_get_dpcd(struct it6505 *it6505, int offset, u8 *dpcd, int num)  in it6505_get_dpcd()  argument
631 	ret = drm_dp_dpcd_read(&it6505->aux, offset, dpcd, num);  in it6505_get_dpcd()
637 			     num, dpcd);  in it6505_get_dpcd()
1448 		return it6505->dpcd[DP_TRAINING_AUX_RD_INTERVAL] >= 0x01;  in it6505_use_step_train_check()
1459 	if (it6505->dpcd[0] == 0) {  in it6505_parse_link_capabilities()
1466 	link->revision = it6505->dpcd[0];  in it6505_parse_link_capabilities()
1467 	link->rate = drm_dp_bw_code_to_link_rate(it6505->dpcd[1]);  in it6505_parse_link_capabilities()
1468 	link->num_lanes = it6505->dpcd[2] & DP_MAX_LANE_COUNT_MASK;  in it6505_parse_link_capabilities()
1470 	if (it6505->dpcd[2] & DP_ENHANCED_FRAME_CAP)  in it6505_parse_link_capabilities()
1491 	it6505->branch_device = drm_dp_is_branch(it6505->dpcd);  in it6505_parse_link_capabilities()
1499 	it6505->enable_ssc = (it6505->dpcd[DP_MAX_DOWNSPREAD] &  in it6505_parse_link_capabilities()
1709 		drm_dp_link_train_clock_recovery_delay(aux, it6505->dpcd);  in it6505_step_cr_train()
1781 		drm_dp_link_train_channel_eq_delay(aux, it6505->dpcd);  in it6505_step_eq_train()
2296 		memset(it6505->dpcd, 0, sizeof(it6505->dpcd));  in it6505_process_hpd_irq()
2352 		if (it6505->dpcd[0] == 0) {  in it6505_irq_hpd()
2353 			it6505_get_dpcd(it6505, DP_DPCD_REV, it6505->dpcd,  in it6505_irq_hpd()
2354 					ARRAY_SIZE(it6505->dpcd));  in it6505_irq_hpd()
2384 		memset(it6505->dpcd, 0, sizeof(it6505->dpcd));  in it6505_irq_hpd()
2700 		memset(it6505->dpcd, 0, sizeof(it6505->dpcd));  in it6505_detect()
2760 		memset(it6505->dpcd, 0, sizeof(it6505->dpcd));  in it6505_extcon_work()
3457 	memset(it6505->dpcd, 0, sizeof(it6505->dpcd));  in it6505_i2c_probe()