337 	regmap_write(priv->regmap, 0x03, 0x04);  in ch7033_bridge_disable()
345 	regmap_write(priv->regmap, 0x03, 0x04);  in ch7033_bridge_enable()
362 	regmap_write(priv->regmap, 0x03, 0x04);  in ch7033_bridge_mode_set()
365 	regmap_write(priv->regmap, 0x52, 0x00);  in ch7033_bridge_mode_set()
367 	regmap_write(priv->regmap, 0x52, RESETIB);  in ch7033_bridge_mode_set()
372 	regmap_write(priv->regmap, 0x03, 0x00);  in ch7033_bridge_mode_set()
382 	regmap_write(priv->regmap, 0x0b, (mode->htotal >> 8) << 3 |  in ch7033_bridge_mode_set()
384 	regmap_write(priv->regmap, 0x0c, mode->hdisplay);  in ch7033_bridge_mode_set()
385 	regmap_write(priv->regmap, 0x0d, mode->htotal);  in ch7033_bridge_mode_set()
386 	regmap_write(priv->regmap, 0x0e, (hsynclen >> 8) << 3 |  in ch7033_bridge_mode_set()
388 	regmap_write(priv->regmap, 0x0f, hbporch);  in ch7033_bridge_mode_set()
389 	regmap_write(priv->regmap, 0x10, hsynclen);  in ch7033_bridge_mode_set()
392 	regmap_write(priv->regmap, 0x11, (mode->vtotal >> 8) << 3 |  in ch7033_bridge_mode_set()
394 	regmap_write(priv->regmap, 0x12, mode->vdisplay);  in ch7033_bridge_mode_set()
395 	regmap_write(priv->regmap, 0x13, mode->vtotal);  in ch7033_bridge_mode_set()
396 	regmap_write(priv->regmap, 0x14, ((vsynclen >> 8) << 3) |  in ch7033_bridge_mode_set()
398 	regmap_write(priv->regmap, 0x15, vbporch);  in ch7033_bridge_mode_set()
399 	regmap_write(priv->regmap, 0x16, vsynclen);  in ch7033_bridge_mode_set()
410 	regmap_write(priv->regmap, 0x1a, mode->clock >> 8);  in ch7033_bridge_mode_set()
411 	regmap_write(priv->regmap, 0x1b, mode->clock);  in ch7033_bridge_mode_set()
414 	regmap_write(priv->regmap, 0x1f, (mode->htotal >> 8) << 3 |  in ch7033_bridge_mode_set()
416 	regmap_write(priv->regmap, 0x20, mode->hdisplay);  in ch7033_bridge_mode_set()
417 	regmap_write(priv->regmap, 0x21, mode->htotal);  in ch7033_bridge_mode_set()
420 	regmap_write(priv->regmap, 0x25, (mode->vtotal >> 8) << 3 |  in ch7033_bridge_mode_set()
422 	regmap_write(priv->regmap, 0x26, mode->vdisplay);  in ch7033_bridge_mode_set()
423 	regmap_write(priv->regmap, 0x27, mode->vtotal);  in ch7033_bridge_mode_set()
437 	regmap_write(priv->regmap, 0x55, hbporch);  in ch7033_bridge_mode_set()
438 	regmap_write(priv->regmap, 0x56, hsynclen);  in ch7033_bridge_mode_set()
444 	regmap_write(priv->regmap, 0x58, vbporch);  in ch7033_bridge_mode_set()
445 	regmap_write(priv->regmap, 0x59, vsynclen);  in ch7033_bridge_mode_set()
453 	regmap_write(priv->regmap, 0x03, 0x01);  in ch7033_bridge_mode_set()
484 	regmap_write(priv->regmap, 0x64, 0x29); /* LSB Blue */  in ch7033_bridge_mode_set()
485 	regmap_write(priv->regmap, 0x65, 0x29); /* LSB Green */  in ch7033_bridge_mode_set()
486 	regmap_write(priv->regmap, 0x66, 0x29); /* LSB Red */  in ch7033_bridge_mode_set()
487 	regmap_write(priv->regmap, 0x67, 0x00); /* MSB Blue */  in ch7033_bridge_mode_set()
488 	regmap_write(priv->regmap, 0x68, 0x00); /* MSB Green */  in ch7033_bridge_mode_set()
489 	regmap_write(priv->regmap, 0x69, 0x00); /* MSB Red */  in ch7033_bridge_mode_set()
497 	regmap_write(priv->regmap, 0x03, 0x03);  in ch7033_bridge_mode_set()
508 	regmap_write(priv->regmap, 0x03, 0x04);  in ch7033_bridge_mode_set()
511 	regmap_write(priv->regmap, 0x10, mode->clock >> 16);  in ch7033_bridge_mode_set()
512 	regmap_write(priv->regmap, 0x11, mode->clock >> 8);  in ch7033_bridge_mode_set()
513 	regmap_write(priv->regmap, 0x12, mode->clock);  in ch7033_bridge_mode_set()
565 	regmap_write(priv->regmap, 0x03, 0x04);  in ch7033_probe()