245 static int chipone_writeb(struct chipone *icn, u8 reg, u8 val)  in chipone_writeb()  function
337 	chipone_writeb(icn, PLL_CTRL(6),  in chipone_configure_pll()
339 	chipone_writeb(icn, PLL_REF_DIV, ref_div);  in chipone_configure_pll()
340 	chipone_writeb(icn, PLL_INT(0), best_m);  in chipone_configure_pll()
373 		chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C);  in chipone_atomic_enable()
375 		chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);  in chipone_atomic_enable()
377 	chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff);  in chipone_atomic_enable()
379 	chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff);  in chipone_atomic_enable()
385 	chipone_writeb(icn, VACTIVE_HACTIVE_HI,  in chipone_atomic_enable()
393 	chipone_writeb(icn, HFP_LI, hfp & 0xff);  in chipone_atomic_enable()
394 	chipone_writeb(icn, HSYNC_LI, hsync & 0xff);  in chipone_atomic_enable()
395 	chipone_writeb(icn, HBP_LI, hbp & 0xff);  in chipone_atomic_enable()
397 	chipone_writeb(icn, HFP_HSW_HBP_HI,  in chipone_atomic_enable()
402 	chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay);  in chipone_atomic_enable()
404 	chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start);  in chipone_atomic_enable()
406 	chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end);  in chipone_atomic_enable()
409 	chipone_writeb(icn, SYNC_EVENT_DLY, 0x80);  in chipone_atomic_enable()
410 	chipone_writeb(icn, HFP_MIN, hfp & 0xff);  in chipone_atomic_enable()
413 	chipone_writeb(icn, DSI_CTRL,  in chipone_atomic_enable()
416 	chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0);  in chipone_atomic_enable()
417 	chipone_writeb(icn, PLL_CTRL(12), 0xff);  in chipone_atomic_enable()
418 	chipone_writeb(icn, MIPI_PN_SWAP, 0x00);  in chipone_atomic_enable()
424 	chipone_writeb(icn, BIST_POL, pol);  in chipone_atomic_enable()
429 	chipone_writeb(icn, SYS_CTRL(0), 0x40);  in chipone_atomic_enable()
437 	chipone_writeb(icn, SYS_CTRL(1), sys_ctrl_1);  in chipone_atomic_enable()
440 	chipone_writeb(icn, MIPI_FORCE_0, 0x20);  in chipone_atomic_enable()
441 	chipone_writeb(icn, PLL_CTRL(1), 0x20);  in chipone_atomic_enable()
442 	chipone_writeb(icn, CONFIG_FINISH, 0x10);  in chipone_atomic_enable()