Lines Matching refs:AST_IO_CRTC_PORT
256 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4)); in ast_set_vbios_color_reg()
258 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); in ast_set_vbios_color_reg()
261 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); in ast_set_vbios_color_reg()
262 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8); in ast_set_vbios_color_reg()
275 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff); in ast_set_vbios_mode_reg()
276 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff); in ast_set_vbios_mode_reg()
278 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00); in ast_set_vbios_mode_reg()
281 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8); in ast_set_vbios_mode_reg()
282 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000); in ast_set_vbios_mode_reg()
283 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay); in ast_set_vbios_mode_reg()
284 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8); in ast_set_vbios_mode_reg()
285 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay); in ast_set_vbios_mode_reg()
286 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8); in ast_set_vbios_mode_reg()
312 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); in ast_set_std_reg()
314 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); in ast_set_std_reg()
316 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); in ast_set_std_reg()
318 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]); in ast_set_std_reg()
349 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00); in ast_set_crtc_reg()
354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp); in ast_set_crtc_reg()
359 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp); in ast_set_crtc_reg()
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp); in ast_set_crtc_reg()
371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f)); in ast_set_crtc_reg()
376 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp); in ast_set_crtc_reg()
381 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05)); in ast_set_crtc_reg()
383 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC); in ast_set_crtc_reg()
384 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD); in ast_set_crtc_reg()
388 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xFC, 0xFD, 0x02); in ast_set_crtc_reg()
390 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xFC, 0xFD, 0x00); in ast_set_crtc_reg()
400 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp); in ast_set_crtc_reg()
409 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp); in ast_set_crtc_reg()
416 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf); in ast_set_crtc_reg()
425 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp); in ast_set_crtc_reg()
434 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp); in ast_set_crtc_reg()
439 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp); in ast_set_crtc_reg()
441 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07); in ast_set_crtc_reg()
442 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09); in ast_set_crtc_reg()
443 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80)); in ast_set_crtc_reg()
446 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80); in ast_set_crtc_reg()
448 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00); in ast_set_crtc_reg()
450 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80); in ast_set_crtc_reg()
459 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff)); in ast_set_offset_reg()
460 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f); in ast_set_offset_reg()
474 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1); in ast_set_dclk_reg()
475 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2); in ast_set_dclk_reg()
476 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f, in ast_set_dclk_reg()
505 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0); in ast_set_color_reg()
506 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3); in ast_set_color_reg()
507 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8); in ast_set_color_reg()
514 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0xe0); in ast_set_crtthd_reg()
515 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0xa0); in ast_set_crtthd_reg()
517 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78); in ast_set_crtthd_reg()
518 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60); in ast_set_crtthd_reg()
520 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f); in ast_set_crtthd_reg()
521 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f); in ast_set_crtthd_reg()
523 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f); in ast_set_crtthd_reg()
524 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f); in ast_set_crtthd_reg()
549 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff)); in ast_set_start_address_crt1()
550 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff)); in ast_set_start_address_crt1()
551 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff)); in ast_set_start_address_crt1()
817 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0); in ast_set_cursor_base()
818 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1); in ast_set_cursor_base()
819 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2); in ast_set_cursor_base()
830 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset); in ast_set_cursor_location()
831 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset); in ast_set_cursor_location()
832 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0); in ast_set_cursor_location()
833 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1); in ast_set_cursor_location()
834 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0); in ast_set_cursor_location()
835 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1); in ast_set_cursor_location()
848 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb); in ast_set_cursor_enabled()
1018 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xfc, 0); in ast_crtc_dpms()
1055 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xfc, ch); in ast_crtc_dpms()
1089 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); in ast_crtc_helper_mode_valid()
1222 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_crtc_helper_atomic_enable()