Lines Matching +full:0 +full:xdc
12 if (!ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING)) in ast_astdp_is_connected()
14 if (!ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD)) in ast_astdp_is_connected()
16 if (!ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS)) in ast_astdp_is_connected()
24 u8 i = 0, j = 0; in ast_astdp_read_edid()
32 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING) && in ast_astdp_read_edid()
33 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS) && in ast_astdp_read_edid()
34 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD) && in ast_astdp_read_edid()
35 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_astdp_read_edid()
40 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, in ast_astdp_read_edid()
41 0x00); in ast_astdp_read_edid()
43 for (i = 0; i < 32; i++) { in ast_astdp_read_edid()
45 * CRE4[7:0]: Read-Pointer for EDID (Unit: 4bytes); valid range: 0~64 in ast_astdp_read_edid()
47 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE4, in ast_astdp_read_edid()
49 j = 0; in ast_astdp_read_edid()
55 while ((ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD7, in ast_astdp_read_edid()
56 ASTDP_EDID_VALID_FLAG_MASK) != 0x01) || in ast_astdp_read_edid()
57 (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD6, in ast_astdp_read_edid()
67 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, in ast_astdp_read_edid()
69 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, in ast_astdp_read_edid()
71 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD))) { in ast_astdp_read_edid()
81 0xD8, ASTDP_EDID_READ_DATA_MASK); in ast_astdp_read_edid()
82 *(ediddata + 1) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD9, in ast_astdp_read_edid()
84 *(ediddata + 2) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDA, in ast_astdp_read_edid()
86 *(ediddata + 3) = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDB, in ast_astdp_read_edid()
94 * equal 0 (mod 256). in ast_astdp_read_edid()
95 * 2. Modify Bytes-126 to be 0. in ast_astdp_read_edid()
97 * follow. 0 represents noextensions. in ast_astdp_read_edid()
100 *(ediddata + 2) = 0; in ast_astdp_read_edid()
106 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, (u8) ~ASTDP_HOST_EDID_READ_DONE_MASK, in ast_astdp_read_edid()
109 return 0; in ast_astdp_read_edid()
112 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_astdp_read_edid()
118 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING))) in ast_astdp_read_edid()
119 return (~0xD1 + 1); in ast_astdp_read_edid()
120 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS))) in ast_astdp_read_edid()
121 return (~0xDC + 1); in ast_astdp_read_edid()
122 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD))) in ast_astdp_read_edid()
123 return (~0xDF + 1); in ast_astdp_read_edid()
124 if (!(ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, ASTDP_HOST_EDID_READ_DONE_MASK))) in ast_astdp_read_edid()
125 return (~0xE5 + 1); in ast_astdp_read_edid()
127 return 0; in ast_astdp_read_edid()
135 u32 i = 0; in ast_dp_launch()
140 while (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xD1, ASTDP_MCU_FW_EXECUTING) != in ast_dp_launch()
148 bDPExecute = 0; in ast_dp_launch()
156 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE5, in ast_dp_launch()
167 u8 bE3 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, AST_DP_VIDEO_ENABLE); in ast_dp_power_on_off()
174 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_PHY_SLEEP, bE3); in ast_dp_power_on_off()
183 u32 i = 0; in ast_dp_set_on_off()
186 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE3, (u8) ~AST_DP_VIDEO_ENABLE, on); in ast_dp_set_on_off()
189 if (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDC, ASTDP_LINK_SUCCESS) && in ast_dp_set_on_off()
190 ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, ASTDP_HPD)) { in ast_dp_set_on_off()
192 while (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xDF, in ast_dp_set_on_off()
266 * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp) in ast_dp_set_mode()
267 * CRE1[7:0]: MISC1 (default: 0x00) in ast_dp_set_mode()
268 * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50) in ast_dp_set_mode()
270 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE0, ASTDP_AND_CLEAR_MASK, in ast_dp_set_mode()
272 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE1, ASTDP_AND_CLEAR_MASK, ASTDP_MISC1); in ast_dp_set_mode()
273 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xE2, ASTDP_AND_CLEAR_MASK, ModeIdx); in ast_dp_set_mode()