Lines Matching refs:armada_reg_queue_set

103 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_HPXL_VLN);  in armada_drm_overlay_plane_atomic_update()
106 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_OVSA_HPXL_VLN);  in armada_drm_overlay_plane_atomic_update()
109 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DZM_HPXL_VLN);  in armada_drm_overlay_plane_atomic_update()
118 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),  in armada_drm_overlay_plane_atomic_update()
120 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 1),  in armada_drm_overlay_plane_atomic_update()
122 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 2),  in armada_drm_overlay_plane_atomic_update()
124 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),  in armada_drm_overlay_plane_atomic_update()
126 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 1),  in armada_drm_overlay_plane_atomic_update()
128 		armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 2),  in armada_drm_overlay_plane_atomic_update()
133 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_YC);  in armada_drm_overlay_plane_atomic_update()
136 		armada_reg_queue_set(regs, idx, val, LCD_SPU_DMA_PITCH_UV);  in armada_drm_overlay_plane_atomic_update()
181 		armada_reg_queue_set(regs, idx, val, LCD_SPU_CONTRAST);  in armada_drm_overlay_plane_atomic_update()
185 		armada_reg_queue_set(regs, idx, val, LCD_SPU_SATURATION);  in armada_drm_overlay_plane_atomic_update()
187 		armada_reg_queue_set(regs, idx, 0x00002000, LCD_SPU_CBSH_HUE);  in armada_drm_overlay_plane_atomic_update()
196 		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_Y);  in armada_drm_overlay_plane_atomic_update()
200 		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_U);  in armada_drm_overlay_plane_atomic_update()
204 		armada_reg_queue_set(regs, idx, val, LCD_SPU_COLORKEY_V);  in armada_drm_overlay_plane_atomic_update()